| With the rapid development of wireless communications,automotive electronics and biomedical fields,the integration requirements for chips are getting higher and higher.It is also driving the development of analog-to-digital converters(ADCs)towards the integration of high speed,high precision and low power consumption.Due to the natural advantages of simple structure,small area and low power consumption,Successive Approximation Register(SAR)ADCs have good adaptability.And the hybrid architecture based on them has become one of the hot spots in ADCs research.Flash ADCs have the strengths of simple structure and high conversion rate.Therefore,the hybrid architecture combined with the two provides a new direction for the development of ADCs.Traditional SAR ADCs are less efficient in sampling and energy.And the number of capacitors that grows exponentially with the number of resolution makes the hardware overhead and chip area large.In view of the above problems,a 12 bit 100MS/s Flash-SAR hybrid ADC is designed,while retaining the low power consumption advantages of SAR ADCs and increasing the slew rate of the circuit as much as possible.The main work of the full text is as follows:(1)A 3bit Flash ADC with a high slew rate is designed.Due to its parallel mode of operation,it can simultaneously quantize 3bit digital codes in one clock cycle.The 3bit Flash ADC is used to replace the high 3bit quantization of traditional serial SAR ADC.This way saves two clock cycles of time and increases the sampling rate of the ADC.(2)The design of a charge-redistributing digital-to-analog converters is completed.The energy efficiency of the ADCs is effectively improved by adopting a novel hybrid switching strategy.The hardware consumption is reduced by adopting the segmented capacitor array technique.And the offset error of the Flash stage comparator is reduced by adding the redundant capacitors between stages.(3)A low-power dual-tailed current dynamic latch comparator is designed.The static path in the reset state is truncated by a sequence switch,effectively reducing the quiescent power dissipation of the comparator.(4)A self-triggering asynchronous sequential logic circuit that does not require a large number of delay circuits is designed.The operating efficiency and stability of the circuit are improved.(5)This paper is designed using SMIC 0.11 CMOS technology.The post-simulation results show that at the operating voltage of 1.2V,when the sampling rate is 100MS/s and the input signal frequency is 45.04 MHz,the SNDR is 69.57 d B,the SFDR is 82.53 d B,the ENOB is 11.26 bit,the power consumption is 5.49 m W and the layout area is 446μm×112μm. |
