Research On Carrier Synchronization And Sample Timing Error Estimation In 60GHz Wireless Communication System

With the gradual development of frequency band around 60 GHz, a variety of standards and applications focus on this band are introduced. This thesis is based on the national 863 project "Research on overall technology and high data rate baseband signal processing technology for the millimeter wave and terahertz". This thesis focuses on carrier synchronization and sample timing synchronization in 60 GHz wireless communication system, which based on the standard of IEEE-802.11 ad. And the FPGA implementation and verification for the sample timing synchronization are made in this thesis.In the beginning of this thesis, the background and development status of the 60 GHz wirless communication system are introduced. And then, a detailed analysis on channel characteristics of the 60 GHz system is provided. After that, the channel model of TGad is introduced. In the second chapter, the frame structure of physical layer and the design scheme of baseband transmitter and receiver are introduced.Carrier synchronization technique for 60 GHz baseband receiver is discussed in the third chapter of this thesis. First of all, the necessity of the carrier synchronization is analyzed. And then, existing algorithm, especially ones based on data aided, are briefly introduced. After that, algorithms based on Golay sequences auto and corss correlation are introduced. And some simulations for these algorithms are made. And finally, a low hardware complexity processing method for this algorithm is discussed.Sample timing synchronization technique for 60 GHz baseband receiver is discussed in the fourth chapter of this thesis. First of all, the necessity of the carrier synchronization is analyzed. And then, the Gardner sample timeing error estimation algorithm is introduced. After that, a sample timeing error estimation algorithm based on Golay sequences corss correlation is introduced. And then, a sample timing error correction algorithm based on linear interpolation is introduced. And some simulations for these algorithms are made. And finally, the FPGA implementation and verification for these alogrithms are made. And the validation results show that the proposed algorithm can meet the design needs of this project.