Back-end Physical Design Of Nand Flash High-speed Interface

As chip integration becomes more and more high,the process dimension becomes smaller and smaller,the difficulty of chip back-end design is increasing.Designing a chip with high performance has become an extremely challenging task for back-end designers.This topic comes from an enterprise project,based on ONFI4.2 protocol,complete a NAND Flash high-speed interface module back-end physical design.This design includes IO unit,hard macro and standard cell.There are 108 IO units,60 hard macro,and about 300,000 standard units in total.The physical design of the back-end of the module is completed by using the Innovus tool for APR.The main achievements of this paper are as follows:(1)Complete the APR work of 12 nm NAND Flash high-speed interface module:floor plan,power plan,place,clock tree synthesis and route.In the floor plan stage,according to the data transmission speed,packaging requirements,determine the position of 108 IO units;The location of the hard macro are determined according to the timing closure requirement.According to the design rule,insert various of physical cell;According to the working frequency of module and route resources,design the power network.In the place stage,rough placement is carried out at first,then the position of the standard cell is optimized by scanning chain recombination,and finally the power and timing on the critical path are optimized.In the phase of clock tree synthesis,clock tree parameters,performance indicators,and clock tree cell types are set at first,and then work on clock tree synthesis.In the route stage,the global route is carried out at first,then the track assignment is carried out,and finally the optimal route is carried out.(2)Repair data path timing skew(special timing)according to ONFI PHY integration rules and design requirements.In the floor plan stage,place the standard cells on the critical path in advance.In the place stage,the delay of data path is constrained by setting the maximum and minimum delay to meet the requirement of delay.In the clock tree synthesis stage,clock signals are created on data paths to meet the requirements of clock skew on data paths.(3)Enter ECO stage,repair the remaining violations.In addition to repairing data path timing skew,conventional timing paths also need to converge under multimode and multi-corner operating conditions.The design results show that the NAND Flash high-speed interface module whose size is 1773.3?m x 765.36?m and working frequency is 600 MHz based on ONFI 4.2 protocol,pass DRC,LEC and ANT check.Through the study of this project,some feasibility and implementation are provided for the challenge of back-end design under deep sub-micron process nodes,especially the timing closure of special timing.