Design Of High Speed Hybrid-SAR ADCs

As a bridge between the Analog world and the Digital world,Analog to Digital Converter(ADC)is widely used in wireless communication,aerospace,instrumentation,intelligent sensing and other fields.In recent years,communication technology advances rapidly,and the endless demand for higher sampling rate drives the continuous development of data converters.The demand for high resolution analog-to-digital converters with good dynamic performance,high sampling rate and intermediate frequency & RF sampling ability has been unabated.For wireless communication,millimeter-wave imaging system,optical communication,cognitive radar,etc.,the resolution of ADC is required to be higher than 10 bits,the sampling rate is greater than100 MHz,and it is gradually developing to GHz.In order to acquire both high sample rate and high resolution,Pipelined architecture is usually the first choice,but its power consumption and area overhead can not be ignored.The Successive Approximation Register(SAR)A/D converters have been widely used in various applications with low power consumption and low cost because of their high charge utilization rate and compact modules.However,constrained by process,the early SAR ADCs sampling rate were always difficult to achieve the communication level.During these years,with the progress of process,benefit from the process compatibility of SAR architecture,SAR ADCs and its hybrid structure are gradually emerging in some high-speed application scenarios.In order to carry out the project,firstly,the development of ADCs at home and abroad was investigated,thus,ADCs were divided into three design orientations: low power consumption,high resolution and high speed,then the development trend was summarized.Furthermore,the ADC solutions and specific technologies of high-speed SAR in recent years are deeply explored,Finally,according to the requirements of the project,two ADCs based on SAR structure are designed: 12-bit 100MS/s Flash-SAR ADC and 9-bit 250MS/s SAR ADC applied to the pipelined-SAR structure.The 12-bit 100MS/s Flash-SAR ADC is manufactured by TSMC 65 nm process.There are the following innovations in this design: a hybrid switching sequence of thermometer code &binary code is proposed,which is conducive to component matching and subsequent implementation of digital auxiliary technology;A high-speed comparator with positive feedback load and dynamic bias technology is implemented to improve the response speed as well as reduce the power consumption;An asynchronous clock logic with automatic optimization delay is designed,which can extend the setting time of reference voltage to the maximum duration and reduce the dynamic error.The post-simulation results show that the ADC has good performance under three representative process corners.In the worst case,SINAD is 71.89 d B,SFDR is 89.26 d Bc,and ENOB is 11.65 bits.The power consumption of ADC core circuit is 5.5m W under 1.2V power supply.The static current of the on-chip reference voltage buffer is 15 m A and the output voltage is 600 m V under 1.2V power supply.The core circuit layout area is 820?m × 740?m.The 9-bit 250MS/s SAR ADC is manufactured by the TSMC 28 nm process,which is different from the separate SAR ADC design,considering that it is the first stage in the composite structure,it needs to pay attention to the swing relationship between the two stages.There are the following highlights in this design: optimize the design of the dual-control path bootstrap to improve the dynamic performance;A comparator with self-calibration module is designed to improve the accuracy.A dynamic level shifter is designed,which has advantages in speed,power consumption and area compared with the traditional structure.Finally,the post-simulation results show that the ADC has good performance under three representative process corners.In the worst case,SINAD is 53.98 d B,SFDR is 72.93 d Bc,and ENOB is 8.67 bit.The power consumption of ADC core circuit is 2.7m W under the condition of 1V power rail.The static current of the on-chip reference voltage buffer is 3.1m A under the condition of 1.8V power rail.The layout area of the core circuit is 210?m × 60?m.