Design Of General Processing Module Of High-rate Multi-standard Vector Signal Demodulator

Nowadays, sharply rising demand for high rate digital communication has promoted the complexity of digital demodulator dramatically. This thesis conducts a research on the architecture of digital demodulator for general purpose, which can processed signals in various modulation formats. The architecture contains two parts, general purpose processing part and dedicated processing part. The thesis focuses on the general-purpose processing part and makes breakthrough in the critical issue of the high-rate demodulation, such as parallel digital resampling, frequency domain parallel matched filtering and timing synchronization.First, an improved parallel architecture for vector demodulation is proposed based on the existing knowledge. Then the thesis highlights the general demodulation processing part. The general part contains the parallel digital resampling, frequency domain parallel matched filtering and timing synchronization. The analysis results show that the improved architecture can demodulate the high-rate vector signals at a lower clock rate, easily constructed in hardware.Second, the thesis researches a high order interpolation resampling algorithm on polynomial fitting by solving the resampling theoretical model. The thesis also analyzes the FPGA implementation of resampling algorithm using the classic Farrow structure in detail. MATLAB simulations verifies the effectiveness of the algorithm at the end.Third, the thesis discusses the implementation of frequency domain parallel matched filtering and timing synchronization. As the multiplying in time domain equals to convolution in frequency, the thesis designs a simplify scheme of matched filtering. Taking advantage of the shift characteristic of the Fourier transform, the thesis achieves timing error correction by multiplying the phase rotation factor in frequency domain. This method greatly reduces the complexity of the timing correction in contrast of time domain.Finally, the thesis conducts the implementation of all proposed parts of the general demodulation processing on FPGA. The experiment results verify that the system can achieve a well demodulation for multi-standard vector signals with its center frequency 720 MHz, such as BPSK、QPSK、8PSK and 16 QAM.