Design Of A 10Bit 0.6-V SAR ADC With Nanowatt Power

As the bridge between analog circuits and digital circuits,analog-to-digital converters（ADC）are widely used.Successive approximation register（SAR）ADCs are popular in low-power applications such as wearable smart devices and implantable biomedical devices due to their simple structure and easy integration,and their high degree of passivation and digitalization make an important way to reduce power consumption is to reduce the supply voltage.However,traditional voltage-domain comparators,the core analog circuitry of SAR ADCs,face significant design challenges at a low voltage.The time-domain comparators such as voltage-controlled oscillator（VCO）-based comparators are a current research hotspot for low-voltage applications,but there is still much space for power-speed co-optimization.This thesis proposes innovative techniques for VCO-based comparators to further optimize SAR ADC energy efficiency,specifically:1)The VCO stage adaptive adjustment technology is proposed to realize the power-speed co-optimization of VCO-based comparator.The existing VCO-based comparators always take a fixed number of VCO stages,result in a speed loss when the input signal amplitude is large.When the input signal amplitude is small,there is a power loss due to the phase detector need to multiple work.Aiming at the above shortcomings,this thesis adaptively adjusts the number of VCO stages for different input signals.The proposed technique configures fewer VCO stages to increase the speed when the input signal is large,and more VCO stages to avoid unnecessary phase discrimination when the input signal is small,which achieves power-speed co-optimization of the VCO-based comparator.2)The VCO reset-in-time technique is proposed to further reduce the VCO-based comparator power consumption.For the traditional application of VCO-based comparator in SAR ADC,the comparator is not reset in time after the comparison result is generated,which consumes large power by still meaningless oscillations.This situation is due to the work of subsequent SAR logic circuits.This thesis proposes the VCO reset-in-time technique to further reduce the VCO-based comparator power consumption by adding a simple logic and latch circuit to reset the VCO immediately after the decision is completed.Based on the techniques above,a 10-bit SAR ADC under 0.6-V supply is designed in this thesis using 0.18-μmCMOS technology.The sampling switch make the sampling accuracy sure by two-stage bootstrap,which provides greater than 80 d B SNR at 0.6-V.The V_cm-based switching scheme provides a constant common-mode voltage for the comparator and is more suitable for low-voltage operation.The designed SAR ADC consumes only 140.42n W at 20 k S/s sampling rate and an area of 0.047 mm²,which achieves an SNDR of 60.61d B and a Fo M of 8.04 f J/conversion-step with parasitic and noise.The proposed SAR ADC is well suit for low-voltage and low-power applications.