The process node of integrated circuit has entered the era of 5nm from 28 nm,and the degree of integration has been greatly improved,which means that more functions can be implemented in the same area,and it also means that the difficulty of chip verification increases with the increase of chip functions.Verification occupies nearly 70%of the design time in the chip front-end design,and it has become the biggest and most time-consuming bottleneck in the entire chip design process.This thesis mainly studies the core of chip verification--digital function verification.It will be combined with a Wireless Body Area Network(WBAN)chip,based on the System Verilog verification language and Universal Verification Methodology(UVM)research,to build a flexible and reliable verification platform.In addition,the functional verification of the WBAN security module is carried out through dynamic simulation and coverage statistics.There are three processes in the first section: to describe the basic process of authentication and encryption,to analyze the security module of the WBAN chip,and to describe the principles and hardware structures of HMAC-SHA256,Elliptic Curve Cryptography(ECC)and Advanced Encryption Standard(AES).Then,there is going to design the authentication and encryption register group,build the register model,and design a set of register configuration scheme.In the end,according to the external interface,to build the Serial Peripheral Interface(SPI)on-board bus verification component,and package it in the top-level environment to complete the construction of the verification platform.After completing the construction of the verification platform,according to the functional requirements of the modules,put forward verification function points,formulate verification plans,construct functional test cases,not only design components for collecting coverage,but also design register scripts that can quickly create register models,and Automated test scripts for test cases can be run automatically to improve verification efficiency,and finally tools are used for debugging and waveform simulation.According to the analysis of the simulation waveform and platform verification results,it is concluded that the SPI transmission is correct,the register model functions normally,and the algorithm operation results are correct.Continue to narrow constraints and add directional incentives based on feedback from coverage reports.The final platform verification report shows that the module function coverage rate reaches 100%,and the code coverage rate exceeds 98.57%,which meets the verification goals. |