The Design Of AES Module Verification Platform Based On UVM

The blow-out development of the integrated circuit industry and the increasing number of chip functions have burdened verification personnel with much workload and difficulty in recent years.The verification is the essential phase of entire chip from design to tape-out,which directly relates to whether the chip can be realized from theory to practice.Driven by the market interests,verification is becoming more matured and gradually forming a certain System.Universal Verification Methodology(UVM)based on System Verilog can greatly improve the efficiency of verification.Each component in the UVM has the clear and distinct functions,including strong dependence and hierarchy.This not only enormously advances the reusability of the verification platform and the convenience of transplantation,but also saves plenty of time and labor,and reduces the cost of verification.Using UVM technology to build verification platform has become the trend of IC design industry.The research of this paper is the AES algorithm module based on the smart card in the company.This paper mainly focus on how to use UVM method to develop a verification program,determine the verification platform structure and improving the efficiency of verification.In the building of the verification platform,first of all,according to the specific function of the bus in the chip,adopt simplified AHB bus function model and package it into sub_enveriment.This could not only improve the reusability of bus function model,but also reduces the difficulty of encoding.And then,constructing the reference model with the same function which is based on the research of AES algorithm protocol.According to the functional division,the author develops the testcases which are interface verification,function verification and abnormal verification with fault injection.Finally,a constrained random excitation is generated by the sequence;driven the sequence by the Driver component;the monitor component completes monitoring and sampling from the interface of the DUT;the scoreboard component performs a comparison between reference model and the output of the DUT.After the verification platform is completed,in order to improve the automation of the entire verification process,corresponding scripts have been developed,including the automatically running of compile commands,the conversion of register document into model and the automatic check of simulation logs.The signs which judging verification tending to the end is coverage.In the late stage of project verification,multiple regressions are required to collect coverage reports under different random seeds.Besides,it's better to adjust constraints and weight distributions to increase the convergence of the coverage..According to the final coverage report,the function coverage reaches to 100% and code coverage reaches to 98.3%,which can be determined that verification of this module basically meet the requirement.