Research And Design Of Key Technologies For High Resolution SAR ADC

In the era of the Internet of Things,higher precision,higher speed,and lower power consumption are required for analog-to-digital converters.Successive approximation analogto-digital converters have the advantages of low power consumption,small area,and simple structure,making them one of the current research hotspots in analog-to-digital converters.This article is based on the application scenarios of high-precision control in the Internet of Things,and studies and designs the key technologies of high-precision successive approximation analog-to-digital converters.This article designs a 12 bits differential input successive approximation analog-to-digital converter with a sampling rate of 10MS/s.The overall framework of the successive approximation analog-to-digital converter is divided into four modules:sampling and holding circuit,CDAC,comparator,and digital logic control.The sampling and holding circuit adopt a gate voltage bootstrap circuit to reduce the overall impact of switch resistance nonlinearity.The simulation results of the designed bootstrap switch circuit show that it has a significant number of 14 bits(ENOB),meeting the design requirements;The DAC capacitor array adopts a charge redistribution type.This article proposes an extended C-2C capacitor array based on the traditional C-2C capacitor array structure.This structure retains the advantages of the simple design of the traditional C-2C capacitor structure and improves its inability to be applied in high-precision ADC,and greatly reduces the capacitance array area compared to traditional binary capacitor arrays,The simulation results of the designed 12 bit extended C-2C capacitor array show that it has 11.9 significant bits,meeting the needs of 12 bit ADC;The comparator adopts a structure combining a pre operational amplifier and a dynamic latch,which improves the response speed of the comparator to small signals while reducing power consumption and noise.The simulation results of the designed comparator show that it can distinguish signals of 0.5LSB,meeting the design requirements;The logic control circuit uses synchronous logic composed of D triggers to complete the function of successive approximation,and simulation results show that it can complete the function of successive approximation and output conversion results.This article designs a differential 12 bits extended C-2C capacitor array successive approximation analog-to-digital converter with a sampling rate of 10MS/s based on the Cadence software platform and UMC 55nm technology,and completes the circuit and layout design.At a 1.2V power supply voltage,a sampling signal of 10MHz square wave,an input signal of sine wave,a common mode level of 0.6V,an amplitude of 0.6V,and an input signal frequency of 4.9707MHz,transient simulation and fast Fourier transform were conducted.The simulation results showed that ENOB was 10.31bit,SNDR was 63.87dB,SNR was 63.88dB,and SFDR was 72.16dBc.In summary,the design goals have been achieved.