| Wide-band RF transceiver chips will improve the integration of the multi-mode multi-standard wireless communication services.The local oscillating signal of the RF transceiver comes from frequency synthesizer,which not only determines the operating frequency range of the transceiver but also affects its reception and transmission performance.Based on the SMIC 55nm CMOS process,this dissertation designs a fractional-N charge-pump phase-locked loop（PLL）with an output frequency range of 6-12GHz,which will provide a high-quality local oscillating signal for most Sub-6GHz wide-band RF transceivers.The main research content of this dissertation is:1)The performance of the oscillator determines the output frequency quality of the PLL.The wide-band voltage-controlled oscillator（VCO）with a single inductor,a switching capacitor array and a varactor array is used to achieve a low phase noise oscillating signal covering 6-12GHz range,and the power consumption and output amplitude of the oscillator can be reconstructed.2)PLL requires a high-speed divider to divide the oscillator output signal.For optimizing the power consumption and highest operating frequency of the divider,this dissertation separately studies the true single-phase clock prescaler and the current mode logic prescaler.It is proposed to use a positive and negative true single-phase clock type latch cascaded D flip-flop in the prescaler,which has a higher operating frequency and lower power consumption than the prescaler composed of the traditional D flip-flop.The divider adopts a pulse-swallowing structure,of which the division ratio can cover 75-1200.3)The integer divide ratio is dynamically switched to achieve a fractional-N division ratio.Aiming at the problem of fractional spurs in the PLL output spectrum,this dissertation uses the Simulink tool to model theΔΣmodulator and study the method of suppressing fractional spurs,and uses the power spectral density of the modulator output sequence to analyze its periodic characteristics and quantization noise.The dissertation proposes a new MASH1-1-1ΔΣmodulator,which can suppress fractional spurious and quantization noise and save circuit component costs.4)In order to optimize the performance of the PLL output signals in each frequency band,the anti-deadzone reset delay of the phase and frequency detector,the current of the charge pump,and the components of the loop filter are digitally controlled,therefore phase-locked loop characteristics can be improved.A wide-band PLL system design method is proposed:the PLL performance is divided into steady-state performance and dynamic performance,in the steady-state error analysis,combined with the Rouse criterion,the loop filter structure can be preliminarily screened;when optimizing the dynamic performance of the phase-locked loop,the open-loop transfer function of the PLL is focused on;this dissertation customizes the MATLAB-based interaction software for the PLL which can quickly draw the loop gain Bode plot,calculate the bandwidth and phase margin,to help users optimize the performance of the PLL.This dissertation completes circuit design,pre-simulation,layout design and post-simulation of the entire PLL on the Cadence platform,and the post-simulation result shows that:1)The high-speed programmable divider can achieve a maximum operating frequency of 17GHz under typical conditions,and under different PVT（Process,Voltage,Temperature）conditions,the 6-12GHz oscillation signal can be divided normally.2)The output frequency of the wide-band VCO covers 6-12.1GHz,the tuning range is about 60%,the（1）ranges from 16MHz/V to 193MHz/V,the output phase noise of the VCO at 6GHz is-112d Bc/Hz@1MHz,and at 12GHz is-102d Bc/Hz@1MHz.The excellent index of the oscillator Fo M is about-170d B.3The anti-deadzone reset delay time of the phase detector is from 0.73ns to 1.26ns,and the step value is 0.177ns.The charge pump is charged or discharged with a total of 64 currents,adjustable from 102μA to 6.53m A,and the dynamic mismatch of all gear charge pump currents is less than 2%.The effective output voltage range of the loop filter is 200m V to 1V,and the PLL can be locked normally at the highest frequency and lowest frequency. |
