Grated Design Of Limiter Low Noise Amplifier With Out-of-band Suppression

With the rapid development of wireless communication technology,communication equipment has higher and higher requirements for the performance and stability of sub circuits such as low-noise amplifier,filter and limiter.The traditional separate design will produce unnecessary performance loss during assembly and connection,which affects the stability and precision of the whole system.Therefore,the demand of wireless communication technology for monolithic integration is higher and higher.This paper is mainly based on the 0.15μm GaAs PHEMT process is used to study a Ka band out-of-band suppression limiter low noise amplifier.In the design,the out-of-band suppression LNA and limiter are designed separately.In this paper,a three-stage structure is adopted for the out-of-band suppression LNA,and a current multiplexing structure is adopted between stages to reduce the current and increase the stability.The filter is not designed alone,but the filter branches are added to the matching network of the low noise amplifier and distributed in the inter stage matching network for reducing the noise loss.In this paper,the limiter adopts an anti parallel two-stage structure,and the thickness of layer I of the first stage PIN diode is 6 × 150um,and three-stage series connection is adopted.The thickness of the second stage Ⅰ layer is 6 × 65um.The input and output of PIN limiter are matched by microstrip line.According to the test results,the operating current is 20mA under 5V voltage,the gain is more than 21dB,the gain flatness is less than±1dB,the ASWRin is less than 2.0db,the ASWRout is less than 2.2dB,the NF is less than 3.6dB,the Pldb is more than 5.5dB at 27.5-31GHz,and the out-of-band rejection ratio is less than-50dB at 17.6-20.6GHz.It has a good out-of-band suppression system,and it can withstand 20 W pulse input power.The development trend of integrated circuits is gradually moving towards monolithic integrated chips.Integrating various circuits into one chip can save more chip area and avoid unnecessary parasitic parameters.