Research And Design Of 12～18GHz GaAs Limiter Low Noise Amplifier

Currently,phased array radar is extensively utilized across sea,land,and air fields.With the development of technology,traditional receiver/transmitter components employing separate connections for limiting amplifiers and low-noise amplifiers are gradually replaced by monolithic integrated limiting low-noise amplifiers,which is aimed at adhering to the trend towards the miniaturization and satisfying higher performance demands.The traditional discrete design is to design and match the limiter and low noise amplifier to 50 Ω separately,and connected by bonded alloy wire and microstrip line.However,the difference in manufacturing processes for these two components increases the difficulty of the assembly and may impact overall performance during the connection and assembly.In addition,the introduction of peripheral matching circuits and gold wires will also increase noise and introduce losses and parasitic parameters to a certain extent.The monolithic integrated limiting low-noise amplifier combines the limiter and lownoise amplifier into a unified design,reducing the chip size while improving overall performance,which effectively addresses the shortcomings of discrete designs.Based on the 0.15 μm Ga As PHEMT process,the thesis designs an integrated chip of limiting low-noise amplifier operating in the Ku-band at 12～18 GHz.The design process involves individual design of the limiter and low-noise amplifier,followed by their cascaded integration and optimization.The limiter consists of a two-stage antiparallel PIN diode structure,with the first stage using a structure which is similar to a power divider and thick I-layer PIN diode which is used to improve the overall power resistance,while the second stage utilizes thin I-layer PIN diodes to enhance response time and reduce peak leakage power.The low-noise amplifier is a three-stage amplification circuit that uses current multiplexing structure to reduce the power consumption.The first stage of the low-noise amplifier is powered by self-bias,which provides convenience for the subsequent power-up of the chip.Besides,a negative feedback is introduced in the third amplification circuit to improve the gain flatness and stability of the circuit.After the two designs are completed,the input matching network of the low-noise amplifier and the output matching network of the limiter are simplified to form an interstage matching network,which replaces the process of direct cascading after the traditional discrete design,and allows the limiter circuit to directly participate in the matching of the low-noise amplifier.Further simulation optimizations are then performed to achieve optimal performance.Finally,tape-out,assembly and testing are carried out.The test results show that when the DC voltage bias is at 5 V,the operating current of the limiting low-noise amplifier is 17 m A.In the frequency range of 12～18 GHz,the gain is26.9～27.8 d B,the gain flatness is better than 0.5 d B,the noise figure is between 1.6 and2.3 d B,the input and output return loss are both more than 11 d B,and the output 1d B compression point is greater than 6 d Bm.