| In recent years,the development of RISC-V open source processors has been very rapid.As an important strategy to improve processor performance,branch prediction focus in the field of RISC-V processor design.Branch prediction can reduce the invalid running cycle of the processor and improve the overall performance of the processor by predicting the jump behavior in the processor.Based on the RISC-V instruction set architecture,thesis conducts optimization research on the G-Share branch predictor.An adaptive branch predictor based on G-Share branch predictor is proposed to solve the compatibility problem of RISC-V processor branch predictors for historical correlation prediction and non historical correlation prediction.The adaptive branch predictor adds local branch prediction to the G-Share branch predictor and selects the prediction results using a state saturation selector,balancing the accuracy of historical correlation prediction and non historical correlation prediction.Based on the consideration of flexible research work,the RV64 IM five-stage pipeline processor was designed and implemented as the research foundation to achieve the optimal design of the G-Share branch predictor.Build a simulation verification platform for processor correctness verification and key performance information acquisition.The single cycle function simulator NEMU is implemented as a reference model for processor comparison.The differential debugging mechanism Difftest performs performance comparison verification and outputs relevant performance indicators for processor runtime.In order to verify the optimization effect,based on the simulation verification platform,the overall performance of the branch predictor before and after optimization is compared.Riscv-tests,CPU tests,and Core Mark benchmark tests are used as simulation run tests.The physical design evaluation of the overall performance of the processor based on the 28 nm process is conducted,mainly including performance,area,and power consumption evaluation.The experimental results show that after optimizing the branch predictor,the processor IPC increases by about 2.7%,and the Core Mark run result is 2.53 Core Mark/Mhz,which increases by about 3%.The processor has a maximum operating frequency of 103 MHz,a total area of 0.13335502 mm2,and a total operating power consumption of 17.6947 m W. |
