Design And Optimization Of Branch Prediction Unit Of Boom Processor

As the demand for computing power grows,various applications place higher demands on the execution efficiency of the processor.For modern processors,their computing power can already meet the needs,and how to "feed" the processor with instructions has become the main contradiction.Therefore,processors are moving in the direction of deep water,superscalar,and multi-core.The penalty caused by mis-prediction of branch prediction units is increasingly unacceptable,which puts forward higher requirements for the accuracy of branch prediction.This paper designs a hardware dynamic two-level predictor based on RISC-V.The expected comprehensive prediction accuracy is greater than 90%.This design plan aims to significantly improve the branch prediction ability of the Boom processor,and at the same time it can solve the Boom processor return address stack)Pollution of the stack.It uses the strategy of classification filtering prediction,adopts different predictors as main predictors for different types of instructions,and also takes into account the prediction time overhead and erroneous prediction penalty.The first-level predictor uses a branch target buffer(BTB).In addition,RAS is added to the prediction of the return instruction to correct the prediction result of BTB.BTB uses the Target partial prediction strategy to reduce the predicted power consumption.The return address stack adds a backup and recovery unit to reduce the probability of misprediction caused by stack pollution.In the second stage of the predictor,the gshare algorithm and predecoder are used to further improve the prediction accuracy of conditional branch instructions.By loading the processor circuit on the VC706 FPGA and running the executable file compiled by the GCC compiler on the system without optimizing.According to the performance counter statistics,the overall average branch prediction accuracy is 92.89%,and the BTB prediction accuracy using partial prediction is 82.04%.By reducing the Tag storage length and adopting the Target partial prediction strategy,it can bring significant reduction in area and power consumption.Among them,the area is reduced by 27.02% before optimization,and the power consumption is reduced by 23.51% compared to before optimization The performance loss is less than 0.6%.The improved return address prediction accuracy is 94.97%,which is an increase of about 45% compared to the RAS prediction without stack pollution repair.This article has made a new exploration of the design of the branch prediction unit of the Boom processor.In particular,a large number of experiments have been carried out on the BTB using part of the Target strategy combined with the pre-decoding structure prediction.The design of the branch prediction unit of the prediction strategy provides data support.The dual stack structure is used to solve the problem of stack pollution when the RAS branch predicts errors,and the prediction performance of the Return instruction of the Boom processor is significantly improved.