Research On Optimization Of RISC-V Processor Core Design And Implementation Of Extened Instruction Set

With the increasing competition in the world semiconductor market,RISC-V has gained widespread attention in the domestic semiconductor industry due to its significant advantages of being open-source and modular.Faced with the current international environment,the domestic semiconductor industry is facing significant challenges,and RISC-V instruction set architecture chips are a key path to achieving chip independence and control.Today,with the diversification of electronic product application scenarios,the requirements for generality,flexibility,and performance of terminal devices are increasing,which poses significant challenges to processor chips.This thesis aims to study the optimization technology of RISCV processor core to improve its generality performance,and to improve its flexibility through hardware additions and compiler modifications of the extended instruction set,in order to better adapt to application requirements in different scenarios.This thesis focuses on the design,simulation,and synthesis of system-on-chip(SoC)chips based on the RISC-V processor.Firstly,the RISC-V CPU pipeline design and implementation methods are studied,and the pipeline architecture of the open-source XuanTie RISC-V processor is analyzed.Secondly,methods and approaches to improve the general performance of the processor are studied,and an improved pipeline architecture called XQ900RV is proposed.For branch prediction and cache modules,solutions are respectively proposed to improve the aliasing problem of the Gshare predictor and cache access optimization technology based on the PLRU algorithm.Next,this thesis discusses the general methods for implementing RISCV extension instruction sets,including the basic schemes of hardware design for extension instruction sets and compiler modification.An extension instruction set supporting SHA2 and SM3 encryption and decryption algorithms is implemented to accelerate the computation of encryption and decryption applications,improve the trustworthy computing performance of the processor,and reduce software power consumption.Finally,based on the XQ900RV processor core,bus matrix and DMA modules are designed,and address space mapping and SoC software development environment are studied.Simulation testing and FPGA prototype verification are conducted to complete the overall design of the SoC.The simulation experiment results showed that in the test of SHA256 extension instruction set implemented in the hardware circuit of the chip,the execution time was reduced by 38%compared to software calculation,and the number of retired instructions decreased by 44%,compared with similar open source processors,it can effectively accelerate algorithm execution.In the FPGA prototype verification,the resource utilization of BRAM is reduced by 21%compared to the initial design by dividing the original program files into 4 banks and storing them in BRAM.The CPU performance was tested using the Coremark benchmark program.Compared to the IPC test results using the static branch predictor,the Gshare branch predictor improved performance by 6.6%,while the branch predictor designed in this thesis improved performance by 9.4%.This indicates that the research presented in this thesis has a significant impact on improving the general processing performance of RISC-V processors,as well as enhancing the flexibility of accelerating processing in trusted computing scenarios.This thesis conducted logic synthesis,power analysis,timing analysis,and formal verification for the entire SoC design.The design achieved a working frequency of 125MHz on UMC 55nm process.The area of the logic circuit is 572144.7μm2,and the power consumption is 48.1399mW.