Research And Implementation Of The Virtual Register Technology In X Microprocessor Based On IA-64

With the rapid development of microprocessor technology, the management and utilization of register technology has taken on a trend of virtualization at present. X microprocessor is a high-performance processor developed by ourself, and completely complatibale with IA-64's architecture. The paper begins with an analysis of IA-64's architecture, then concretely researches and implements the virtual register technology in X high-performance microprocessor, and at last presents a novel mapping-table-based implementation method of RSE (register stack engine) technology.The virtual register technology in X high-performance microprocessor mainly includes regiseter renaming and RSE. The paper detailedly introduces two methods of the regiseter renaming in X high-performance microprocessor, respectively implemented through register rotation and register stack, give an example to show how software pipelining supported by register rotation overcomes the disadvantage to code optimization induced by traditional unloop method, and furthermore implements the renaming design of general register, floating point register and predication register. In respect of RSE, the paper thoroughly studys its implementation condition and process for exchanging data between physical registers and memory, gives the actual design implementation of its finite state machine and functional unit.Design verification is one of the main means to insure the correctness of function and timing. After simply introducing many general verification methods, this paper verifies regiseter renaming and RSE functional units at two different levels. On the one hand, the two functional units is separately verified at module level; On the other hand they are integrated into CPU core , then verified as parts of entire X high-performance microprocessor at system level. The latter is implemented through comparing the two different results from Ski IA-64 hardware simulator and Verilog-XL logic simulator.RSE technology has been implemented efficiently in Itanium microprocessor, but a physical register which has been useless in a procedure can not be released until the procedure is over. This paper presents a novel mapping-table-based implementation method of RSE technology, which maps continuous virtual registers to incontinuous physical registers. A physical register may be freed in time only if it is not required any more in a procedure, so that the register resource will be utilized higher efficiently. This method is completely compatible with IA-64's architecture and supports some important technology such as register rotation and software pipelining.