40GSPS Data Acquisition System Waveform Error Calibration And Feature Search

The rapid development of modern electronic information technology needs to capture the complex electrical signals with high bandwidth and analyze its feature precisely.This requires a data acquisition system with higher bandwidth,higher sampling rate,and stronger data processing function to perform fast feature search and analysis on a large amount of waveform data,and mark and display waveform feature information.Under the condition of the limited performance of the existing Analog-to-Digital Converter(ADC),the time-interleaved sampling technique is one of the most effective methods to increase the sampling rate of the data acquisition system.However,in the time-interleaved parallel acquisition system,the parallel sampling data will have synchronization errors due to sampling clock offsets,different delays of data transmission and storage.At the same time,due to the discreteness of the ADC sampling process and the inconsistency of the frequency response of each acquisition channel when the frequency changes,parallel sampling data will generate mismatch errors,which will eventually lead to the degradation of system sampling performance and affect the accurate realization of the waveform feature search function.This thesis designed and implemented a 40 GSPS data acquisition system through parallel synchronization error calibration and parallel mismatch error calibration,based on the time-interleaved sampling architecture constructed by eight 5GSPS ADCs.At the same time,this thesis designed a scheme to implement fast waveform feature search function.The main contents are as follows:1.Designed a calibration scheme for parallel synchronization errors of multi-ADC sampling,data transmission and storage,and combined with built-in calibration sources to achieve self-calibration of system synchronization errors.First of all,designed a delay adjustment circuit of multiple sampling clocks and ADC reset signals for self-calibration of the acquisition synchronization error of multiple ADCs,so as to achieve correct timeinterleaved sampling of multiple ADCs.Then,designed a parallel data receiving and storage synchronous self-calibration module based on delay traversal search to achieve synchronous self-calibration of multi-ADC sampling data transmission and storage in multiple FPGAs.2.The static and dynamic frequency response mismatch errors in the timeinterleaved sampling system were fully calibrated through two mismatch error calibration schemes,hardware and digital.For the static mismatch error,the built-in calibration source was used to estimate the mismatch error first,and then automatically fed back to adjust the control parameters of gain,offset and time of the sampling front-end hardware,so as to achieve hardware self-calibration of the static mismatch error.Aiming at the dynamic frequency response mismatch error,designed and optimized a digital filter calibration method of "FFT-Frequency Domain Filtering-IFFT" to achieve fullbandwidth dynamic frequency response mismatch error calibration,which improves system sampling performance and reduces logic resources consume.3.Designed a fast waveform feature search scheme based on large-capacity data,and through software and hardware collaborative control,achieved various complex types of fast waveform search such as edge features,pulse width features,and event cascades.Finally,a comprehensive test and verification was carried out in the 40 GSPS data acquisition system.The test results show that the spurious-free dynamic range of the system in the full bandwidth range of 0～3.5GHz is increased to more than 40 d B,and the effective number of bits is increased to more than 5bit,especially when the 3.5GHz sinusoidal signal input is increased by 24.6d B and 2.2bit.The speed of waveform feature search can reach up to 300Mpts/s,the maximum support for 1Gpts sampling point search,and the accuracy is ±25ps.