| With the rapid development of electronic information technology,the signals that need to be measured and analyzed show high-frequency,high-bandwidth and transient characteristics,which requires the acquisition system to have higher bandwidth,sampling rate and storage depth.Due to the limited index of ADC itself at present,the single-chip ADC cannot meet the index of system sampling rate.Therefore,establishing a parallel architecture of a time interleaving acquisition system has become an effective method to improve the sampling rate of the system.However,the parallel acquisition architecture has high requirements for synchronization between multiple devices,and inconsistencies between different sampling paths can lead to system mismatch errors.In addition,in broadband acquisition systems,imperfect frequency response can also generate errors,limit system performance,and make it difficult to accurately reconstruct the original input signal.This thesis focuses on the above issues,and the main content is as follows:1.Implementation of system multi-channel synchronous sampling clock.A threelevel clock tree architecture has been designed to provide multi-channel adjustable delay synchronous clocks,meeting the system’s requirements for sampling clocks.2.Implementation of high-speed parallel data synchronous reception and mass storage.Designed a data series to parallel conversion architecture and path delay selftuning control to solve the problem of high-speed data synchronization reception;Design a multi ADC data path clock synchronous reset module to ensure data reception,storage,and assembly synchronization between multiple FPGAs;Designed a large capacity storage solution based on DDR3,expanding the storage depth of the system.3.System error correction scheme design.This thesis conducts classification analysis and correction of system errors,designs hardware self correction algorithms in conjunction with software to correct fixed mismatch errors,and improves error correction efficiency;A sampling non-uniformity error correction scheme was designed based on the digital time alternating sampling model,which solved the problem of error changing with the frequency of the input signal and ensured the collection performance of the system in the high frequency range;Using estimation methods to obtain the differential frequency response between the amplitude frequency and phase frequency responses of the system and the ideal system,and correcting the error through cascaded filter banks.4.Implementation and optimization of frequency domain error correction hardware architecture.Adopting a master-slave path correction structure based on overlapping frames in the frequency domain,filtering is implemented in the frequency domain to ensure real-time error correction;Design a frequency domain extraction algorithm to reduce the number of IFFT points to one fourth of the data frame,solving the problem of excessive error correction computation and hardware resource consumption.In this thesis,a four-channel time alternation acquisition system is realized through the above scheme.After the test,the sampling rate of the system is 40 GSPS,the input bandwidth is 5.4 GHz,and the storage depth is 4 Gpts.After the mismatch error correction,the SFDR in the full bandwidth of the system is increased by 12.23 dB on average,the effective digit is increased by 1.35 bits on average,the amplitude frequency response fluctuation is reduced from 4.71 dB to 0.91 dB,the rise time is increased from 86.02 ps to 72.99 ps,and the system performance is greatly improved. |
