A Research Of TI-ADC Mismatch Error Calibration Technique Based On Compressed Sensing

With the development of radar,communications and measuring instruments,the system requirements for the accuracy and speed of analog-to-digital converters(ADC)continues to improve.High-speed and high-precision ADC,as a key component in related fields,is also a research hotspot in recent years.As the mainstream structure for realizing high-speed and high-precision ADCs,time-interleaved ADCs can further increase the conversion rate after being combined with compressed sensing.However,the time-interleaved ADC combined with compressed sensing is also limited by the mismatch error,resulting in a significant drop in its performance.Based on the theory of compressed sensing,the thesis carried out related research on time-interleaved ADC mismatch error correction technology.After introducing and analyzing typical mismatch errors and correction algorithms,this paper proposes a time-interleaved ADC mismatch error calibration technique based on compressed sensing.Under the condition of sinusoidal signal input,the proposed technology can correct four typical mismatch errors at the same time and does not require an additional reference channel.Based on compressed sensing,the calibration technique reconstructs the under-Nyquist quantization result with restricted sparsity,and obtains the sinusoidal signal that is closest to the quantization result.The reconstructed signal is used as a reference,and the LMS algorithm and the minimum value function method are combined for calibration.According to the MATLAB numerical simulation results,for a given set of mismatches,the proposed calibration method increases the effective number of bits(ENOB)from 4.5 bit to 11.2 bit,and the spurious free dynamic range(SFDR)from32.5 d B to 80.1 d B.Then,this paper proposes a channel randomization method based on compressed sensing.This method can further improve the SFDR performance of the time-interleaved ADC.Using the feel channels obtained by under-Nyquist sampling avoids the disadvantages of traditional channel randomization methods that need to add additional redundant channels.Numerical simulation results show that the performance of this method is similar to the traditional randomization method that adds a redundant channel.Under a given mismatch error condition,this method improves the SFDR performance by 13.8 d B.Finally,based on the 40nm CMOS process,the digital circuit front-end and back-end design of the proposed calibration algorithm is completed,and the resulting layout area is 0.36mm~2.The behavioral model of time-interleaved ADC is built using System Verilog language,and the calibration performance of the implemented digital circuit is simulated.The results show that under the conditions of 2%capacitance mismatch,20m V offset mismatch,3%gain mismatch,and 15ps sampling time mismatch,the ENOB after calibration is increased from 4.5 bit to 10.9 bit,and the SFDR is increased from 32.68 d B to 73.35 d B,which verifies the realizability and effectiveness of the proposed calibration method.