Design Of A High Speed And High Energy Efficiency ADC Based On 65nm CMOS Technology

The analog-to-digital converter(ADC)is a circuit system that converts analog signals into digital signals.It is widely used in oscilloscopes,radars,digital communicateons,and communications testing equipment,and plays an important role in the production and life of the modern information society.With the development of mobile Internet and Internet of Things technologies,the demand for high-speed and low-power ADCs is getting higher and higher,it is of great engineering and academic value to design a ADC with high-speed and high-energy-efficiency characteristics of medium resolution.This paper designs a 400MS/s 10 bit 2bit/cycle SAR ADC based on 65 nm CMOS process.The structure of 2bit/cycle SAR ADC combines the high energy efficiency of SAR ADC and the high-speed conversion characteristics of FLASH ADC,which can achieve the design goal of high speed and energy efficiency.This paper first analyzes the influence of various non-ideal factors such as comparator offset and CDAC capacitance mismatch on ADC performance through behavioral modeling of ADC,and calculates some key parameters,and then designs the ADC circuit.The entire ADC circuit includes a bootstrap sampling switch,a dynamic comparator with a self-calibration module,two kinds of CDAC(SIG-CDAC and REF-CDAC),an asynchronous clock circuit,and a logic control circuit.Among them,the sampling switch adopts the gate voltage bootstrap structure to improve the speed and linearity.In the design of the CDAC circuit,the non-binary redundancy algorithm is used in this paper to improve the conversion accuracy,and the segment capacitor and split capacitor technology are used to reduce the chip area and power consumption,and keeping the common-mode level of the comparator input unchanged to improve stability.The dynamic comparator adopts a dual-tail current type dynamic comparator structure with a pre-amplifier stage to reduce power consumption and noise and increase speed,and offset calibration is performed by a self-calibration circuit.This paper designs and uses asynchronous clock to improve the conversion speed of ADC.The logic circuit is designed with high speed and low power consumption to improve the speed of the overall ADC circuit.This paper has completed the schematic design,layout design,and pre-simulation and post-simulation of the overall ADC circuit.The layout area(including the pads)is 783mμm×717μm.The post-simulation results(tt,27°C)show that the design in this paper achieves an ENOB of 9 bits at a sampling rate of 400MS/s.The INL and DNL are 0.95 LSB and0.58 LSB respectively,the power consumption is 19.3m W under the 1.2V power supply voltage,and the FOMw reaches 94.2f J/conv-step,which meets the design specifications and reflects the characteristics of high speed and high energy efficiency.The 10 bit 400MS/s SAR ADC designed in this paper has high energy efficiency,high sampling rate and medium precision,so it can be used as a sub-ADC in the ADC of the timeinterleaved architecture to improve the overall performance of the time interleaving ADC;It can also be used as a single-channel ADC in systems with high-speed,low-power,and medium-resolution requirements.