Design And Implementation Of High Energy Efficiency Adaptive Scaling Circuit

In order to solve the energy efficiency requirements of different high-performance SoC chip applications,the ultra-wide voltage range circuit proposed in recent years has received extensive attention.It usually covers the near/sub-threshold region to the conventional voltage region,and can meet the high-performance requirements at high load and the high energy efficiency at low load.As the operating voltage enters the near-threshold region,the problems of timing variations become more significant.To achieve timing variation tolerance at the architecture level,the first key issue is how to detect timing variations in real-time.On the basis of detection,the second key issue is how to achieve timing variation tolerance and ensure correct function under wide voltage range with low overhead.In this paper,some solutions to the problems existing in the direct monitoring(including predictive and error-detect-and-correct types)of adaptive voltage design are proposed.Finally,for the energy-efficient binary neural network accelerator,the online monitoring of the neural network is realized and further improved energy efficiency.The main innovation work is as follows:1.A wide-voltage half-path monitoring method is proposed to solve the problem that predictive monitoring design cannot respond in the current clock cycle.Transition-detectors are inserted in the half of critical paths in order to monitor the on-chip timing information in real time.In this paper,a 9-transistor transition-detector unit(named TD-1)is proposed which can work stably over wide voltage range with small area overhead.Considering the effectiveness of critical paths over wide voltage range,the endpoint covering method is proposed to select the critical paths.The minimum path algorithm is further proposed to select half-path monitoring points that meet the design requirements.The whole design scheme is taped out and verified under SMIC 40nm process.The experimental results show that the maximum energy saving is 50.5%at near threshold,and the whole system can work stably from 0.44V to 1.1V.2.The combination of pulse_latch technology and adaptive voltage design technology are proposed to solve the proplem of error-detect-and-correct design in the direct monitoring of adaptive voltage design.A pulse-generator circuit is used to generate a stable pulse as a clock signal of the latch and the transition-detector.When the timing of the circuit is tense,the time borrowing characteristic of latch is effectively utilized to ensure that the digital circuit design does not have a true timing error.In this paper,a transition-detector unit(named TD-2)is designed with fast response and stable operation under wide voltage range.In order to reduce the area overhead of adaptive voltage design,the pulse_latch clustering algorithm is proposed to reduce the number of pulse-generator circuits as much as possible.The whole design scheme is fabricated in SMIC 28nm technology.The measured results show that the maximum energy gain achieved at 0.55V reaches 64.3%,and the number of buffer insertions is greatly reduced.3.A binary neural network online monitoring methold based on analog delay is proposed.The neural network fault tolerance and adaptive voltage design technology are combined to monitor the timing of the chip and eliminate the timing margins reserved in the design,which can further improve the neural network efficiency.By performing effective timing monitoring on the critical paths in the PE array,when the error rate reaches a certain value,the approximate calculation is used instead of the actual calculation way,which can further reduce the chip's working voltage and improve the energy efficiency of the whole network.The entire binarized neural network design uses the TSMC 28nm process to accomplish a complete design and verification flow from RTL to GDSII,with a layout area of 1.35×1.92 mm~2.The experimental test results show that the energy efficiency of the chip is 6.17 TOPS/W at a normal voltage of0.9V.When the voltage of the chip is reduced to 0.42V,the energy efficiency is increased to51.5TOPS/W.When the adaptive voltage design is turned on,the chip's power saving reaches45.5%at 0.56V.4.The method of cutting the carry chain is proposed as the timing error handling mechanism for the self-accumulation neural network.The simulation results show that the energy consumption of the chip reaches 53.8%at 0.55V and 25?.In a word,the predictive and error-detect-and-correct workload of the direct monitoring scheme proposed in this paper can effectively reduce power consumption and improve energy efficiency.At the same time,the adaptive voltage is applied to the neural network,which effectively improves its energy efficiency.