The Research And Implementation Of LDPC Decoder For Satellite Communications

As an important member of channel coding scheme,Low Density Parity Check(LDPC)codes are widely used in satellite long-distance communication due to their good error correction performance,mainly including Quasi-Cyclic Low Density Parity Check(QCLDPC)codes and Irregular Repeat Accumulate Low Density Parity Check(IRA-LDPC)codes.With the expansion of satellite communication capacity,how to complete high-speed communication with limited communication time and satellite hardware resources poses a challenge to the application of LDPC codes.In this thesis,the QC-LDPC decoding technology in the communication satellite receiver decoder and the FPGA design and implementation of the DVB-S2 X standard decoder are analyzed and studied,and the decoding algorithm and hardware implementation scheme are carried out to make full use of the limited resources.Satellite communication platform for efficient implementation of decoders.The main work of the thesis includes:(1)A low-complexity and high-throughput decoder design based on QC-I LDPC codes is proposed,and a coderate compatible technology is proposed for variable coding and modulation.This structure can correctly switch 7 kinds of coding and modulation modes.Aiming at the problem of decoding performance loss caused by soft information quantization,a quantization optimization method based on amplitude is proposed,which speeds up bit error rate reduction in fixed point implementations.Field Programmable Gate Array(FPGA)test results show that the decoder has a throughput rate of 875 Mbps under a 200 MHz operating clock and supports variable coding and modulation(VCM)mode.(2)The high-speed FPGA implementation of the QC-Ⅱ LDPC code in the Consultative Committee for Space Data Systems(CCSDS)standard is carried out.Aiming at the data congestion caused by the high row weight of the sub-matrix of the check matrix of the QC-Ⅱ LDPC code,a hierarchical grouping method is adopted,and a QC-Ⅱ LDPC partial parallel decoder structure is proposed.The realized partial parallel and fully parallel decoders can work stably under the 200 MHz operating clock,and the throughput rates reach 987 Mbps and 2105 Mbps respectively.(3)With the change of the communication standard,the orbiting satellite will not be compatible with the new standard,so a configurable LDPC layered-decoding structure is proposed.By abstracting the decoding process as the decoding instruction set to call various computing and storage resources,the hardware circuit is no longer associated with the specific parameters of the LDPC code.The FPGA implementation shows that the decoder has a throughput of 1191 Mbps.(4)Aiming at the requirement of many kinds of modulation constellations and high modulation order in DVB-S2 X standard,a low-complexity parallel soft demapping scheme that supports all amplitude-phase shift keying modulation modes in the standard is proposed and implemented.It has a throughput rate of 200 Msps under a 200 MHz working clock,and a throughput rate of 1.6Gbps under the 256 Amplitude Phase Shift Keying(APSK)modulation mode.In the FPGA download test,the LDPC decoder is cascaded to verify its correctness.For the IRA-LDPC code in the DVB-S2 X standard,a parallel node information update array structure is proposed.