High Throughput LDPC Encoder And Decoder Hardware Design

Mobile communication is one of the most promising branches in the communication area. In the next generation communication system, in order to satisfy the ever increasing high-quality requirements for high-speed data transmission, we need to further improve the existing key techniques in the physical layer. For instance, As a result of the superior error-correcting abilities and efficient iterative decoding algorithms of LDPC codes, they have become the focus of coding community once again.QC-LDPC code is an architecture-aware LDPC code and is created by circular right shift based on some base matrixes. These features make the design of LDPC codes'encoder and decoder much simpler and have higher parallel degree and decode throughput. Here we introduce some classical algorithms of LDPC encoder and decoder, especially Efficient encoding algorithm. Some decoding algorithms including Belief Propagation (BP) decoding algorithm in probability domain, Log-domain and modified Min-Sum decoding algorithm are introduced on the base of understanding massage passing algorithm. Analyzing three types of decoder architectures including: fully parallel architecture, serial architecture and partial parallel architecture on the base of FPGA hardware design, and finally giving the decoder algorithm we used in the hardware design.The hardware design of FEC implements encoding, noising, quantization and decoding. For specific architecture-aware QC-LDPC, using Efficient encoding algorithm, during the process of encoding, two frames codes are in the encoder doing ping-pong operation, in order to improve encoding efficiency. Random number is generated according to the specific random-number-generate algorithm, which is used to simulate AWGN to implement noising process. According to the specific quantization diagram mapping 4bit number into n bit LLR as the input of decoder. The decoding algorithm of the design is modified Min-Sum decoding algorithm based on Layered-Decoding. Generally, considering the factors such as the resource of Stratix IV EP4SGX530 Chip, the timing constrain and the design requirements and so on, each decoding module includes four decoding chips, and each decoding chip implements two frames codes'Layered-Decoding. The whole design of FEC implements throughput is 3Gbps, the frequency is 250MHz, the bandwidth is 12bit and the fixed maximal iterative number is 14.