The Research And Design Of The Structure Of The All-Digital Phase-Locked Loop

The application of PLL is in the fields of communication,control and electronic information technology,while the all digital PLL has gradually replaced the analog PLL in many aspects.The stability of the all digital PLL is better,it is easy to integrate,and its reliability is higher.It also solves many problems of the analog PLL,such as weak anti-interference ability,easy to be affected by environment and temperature,DC zero drift and device saturation Defects.Nowadays,digital technology has become more and more mature.Therefore,all digital PLL has attracted more and more attention of scholars in the world.The key issues to improve the performance of all digital PLL are the improvement of PLL range and PLL speed,and the reduction of total power consumption of the system.Two new all digital PLLs are proposed to solve the problems of narrow PLL range,slow PLL speed and high total power consumption.One is to replace the traditional accumulator circuit structure with the variable phase accumulator structure.The digital phase discriminator of the loop adopts the forward zero crossing phase discriminator,and the internal delay link is composed of a group of D flip-flops.The digitalloop filter and the digital controlled oscillator adopt the structure of variable phase accumulator.This kind of PLL can enlarge the PLL range of the loop system and reduce the total power consumption of the system;the other is the third-order all digital PLL with the circuit structure of the fast accumulator.The integrator and the numerical control oscillator in the digital loop filter of this system adopt the circuit structure of the fast accumulator.This paper studies the mathematical modeling of the proposed phase-locked system,obtains the conditions to keep the system stable through theoretical analysis,analyzes the steady-state performance of the system,selects the appropriate steady-state parameters,builds the simulation model in MATLAB software platform,verifies the theoretical analysis results,and completes the loop system successively by using electronic design automation technology Based on the model SIM simulation platform,a hardware test platform is built to realize the phase-locked function.Compared with the traditional all digital phase-locked loop,the all digital phase-locked loop with variable phase accumulator structure improves the phase-locked frequency of the system,expands the phase-locked range,reduces the total power consumption of the system under the condition of not occupying much internal logic resources of the chip,and its phase-locked range is 0.06mhz-3.92mhz;another all digital phase-locked loop with fast accumulator circuitstructure,its phase-locked range is 0.03 m In the range of Hz ~ 7.84 mhz,the signal can be locked completely in one input signal cycle as soon as possible.The PLL has the advantages of fast speed,wide range and high stability.