Research And Design Of A Fast Adaptive All Digital Phase-locked Loop

This paper mainly focus on studying for a new type of adaptive-bandwidth Alldigital phase-locked loop. On one hand, the system, whose loop bandwidth can beautomatically adjusted following the frequency of the input signal frequency,is basedon adaptive PI control strategy, thus it has a larger phase locking range; on the otherhand, The loop filter parameters can switch between the fast acquisition mode, buffermode and locked mode according to the size of the phase error, namely the loopbandwidth can be automatically adjusted with the size of the phase error,so it canovercome the contradiction between the loop capture speed and the noise resistanceeffectively. The implementation of the loop parameters adopts the design method ofdigital shift addition, it can greatly simplify the circuit structure compared with thetraditional method realized by using dividers. And the phase-locked loop formedentirely by digital module can overcome flaws such as voltage-controlled oscillatorinherent nonlinear, phase discriminator low accuracy, devices easy to saturation andhigh order system unstable defects compared with the analog phase-lockedloop,which gives the system features like high parameter stability, high reliability andeasy to integration, etc.On the basis of in-depth study about the theoretical model and implementationstructure of the phase-locked loop, the whole system circuit was finally realizedthrough the top-down modular design technology.The related comprehensivesimulation was carried out by QuartusII software environment, and a series ofperformance analysis under different loop control parameters was compared. Finallythe design program was downloaded to the device EP1C6Q240C8FPGA of Alteracompany to realize the hardware implementation. System simulation and hardwaremeasurement showed that: the control mode combined adaptive PI control withdynamic PI control, makes the loop bandwidth possess a real-time control with boththe change of the input signal frequency and the phase error. When the system clock is 60MHz, loop adjustment time is approximately8input signal cycle, overshootamount to4.32%, track locking range is40Hz-1MHz.System performance andtheoretical analysis are highly coherent.