Study Of Dynamic Hot Carrier Degradation Of Poly-Si TFTs And Optimization Of Their Degradation Suppression Structure

In recent years,with the continuous development of flat panel display devices,new smart terminals represented by VR glasses have put forward higher requirements for display devices.In order to get a better and more realistic experience,the refresh rate of the display device on the VR glasses needs to reach 120～240 Hz,and the resolution should reach 4K一 16K.Therefore,as a widely used key component in flat panel display circuits,polycrystalline silicon thin-film transistor(Poly-Si TFT)devices will operate under higher and higher frequency.As the operating frequency increases,the pulse period applied to the device becomes shorter,and the corresponding pulse rising and falling edge also become steeper.Studies have shown that when a TFT is subjected to pulse with a rising and falling edge time of sub-microsecond,its electrical characteristics will be significantly degraded,thereby affecting the life of flat-panel display devices.Taking the degradation of poly-Si TFT under dynamic gate pulses as an example,previous studies have shown that the degradation is related to the gate pulse frequency,amplitude,and falling edge time.The higher the frequency,the larger the amplitude,and the shorter the falling edge time,the more severe the degradation.In addition,it is generally observed that the degradation is closely related to the falling edge of the pulse,but there is no consistent conclusion about the relationship between the rising edge and the degradation.The research in this paper finds that for dynamic gate pulses,taking the flat-band voltage of the device as the boundary,pulses with different amplitude ranges have different dependencies on the rising and falling edges.When the gate pulse amplitude range is above the flat-band voltage,the device has no degradation;the gate pulse amplitude crosses the flat-band voltage,that is,the OFF-ON pulse,and the degradation is related to the falling edge of the pulse and has nothing to do with the rising edge;the gate pulse amplitude is within or below the flat-band voltage,that is,under the condition of OFF pulse,the device degradation is related to both the rising and falling edges of the pulse.Based on the nonequilibrium PN junction degradation model previously used to explain the falling-edgerelated degradation,combined with Silvaco TCAD transient electrical simulation,this paper proposes a rising-edge-related dynamic degradation mechanism.The non-equilibrium expansion of the depletion region of the PN junction is also found after the rising edge of the off-state gate pulse,and the degradation caused by the rising edge can also be explained by the non-equilibrium PN junction degradation model.Therefore,the degradation models related to rising and falling edges are unified in this study.In order to suppress the dynamic degradation of polycrystalline silicon thin film transistor devices,a four-terminal thin film transistor including a carrier injection terminal was proposed by our group.Based on this,this paper optimizes its structure to obtain better degradation suppression effect.By changing the width of the carrier injection terminal and the distance between the carrier injection terminal and the drain,the capability of degradation suppression can be adjusted.In this paper,combined with the channel coupling potential under dynamic gate voltage,the effect of the expansion of the depletion region of the PN junction at the drain on the degradation suppress processes is analyzed.Through Silvaco TCAD simulation and combined with the experimental results,the process of degradation suppression under different conditions is analyzed in detail.The carrier injection terminal suppress the degradation based on two mechanisms.On the one hand,the injected carriers diffuse to the boundary of the depletion region of the drain,weakening the electric field of the depletion region,and on the other hand,the injected carriers can trap deep-level defect states in the channel to prevent non-equilibrium emitted carriers from entering the depletion region to form hot carriers.The reason why the degradation suppression effect is weakened when the carrier injection terminal is adjacent to the drain is analyzed.The influence of the expansion of the drain depletion region on the degradation suppression at the instant of falling edge is clarified,and the optimal design of the degradation suppression structure is given.When the carrier injection end is located in the center of the channel side,the wider the carrier injection terminal,the better the suppression.When the width of the carrier injection terminal remains unchanged,the degradation suppression effect is the best when its boundary coincides with the boundary of the PN junction depletion region at the drain terminal at the end of the falling edge.