Design And Analysis Threshold Voltage Detection Algorithm For MLC NAND Flash Memory

With the advent of the Internet of Things,massive data storage has attracted extensive attention.NAND flash memory,as a novel storage medium,has attracted much attention.Benefiting from the characteristics of large capacity,high read-andwrite speed and low consumption,NAND flash memory has been widely utilized in a myriad of data storage applications,such as solid-state disk(SSD).NAND flash memory has become an outstanding representative of non-volatile memory(NVM)mainly because of the reduction of memory chip size and the development of multilevel cell(MLC)technology,so that a single memory cell stored multiple bits.With the size of NAND flash memory chips scaling down,the flash memory suffers from severer circuit-level noise,leading to lower reliability and shorter lifetime.Therefore,this thesis is devoted to the design and analysis of new threshold voltage detection schemes that can improve the reliability of the NAND flash memory.The main content of this dissertation includes the introduction of deep learning technology,the optimization of log likelihood ratios(LLR),read-voltage design,the design of cell-tocell interference elimination scheme and so on.The main research works of this thesis can be described as follows:(1)The threshold voltage detection scheme is studied in MLC flash memory system.To accurately acquire the LLRs without the knowledge of the thresholdvoltage distributions,a convolutional neural network(CNN)-based detection algorithm is proposed for MLC flash memory.The CNN architecture is trained to predict the a-posteriori probabilities of the four threshold-voltage states.Furthermore,the CNN-based detection algorithm employs the average a-posteriori probabilities to calculate accurate the LLRs for each threshold-voltage region.Since the threshold voltages continue changing over different PE cycles and retention time,it is necessary to design the read voltages for adapting to the variation of the flash memory channel.To this end,we develop a CNN-aided read-voltage design scheme to optimize the read voltages by maximizing the mutual information between the coded bits and their corresponding LLRs.Simulations results demonstrate that the proposed CNN-based detection algorithm and CNN-aided read-voltage design schemes can achieve performance approach that of the optimal detection algorithm.(2)To alleviate the CCI caused by the effect of parasitic coupling capacitance between adjacent cells,we present two CCI-mitigating schemes to eliminate the CCIinduces errors for MLC flash memory,referred to as vertical-and-diagonal direction correction(VDDC)detection scheme and all-direction correction(ADC)detection scheme.The basic idea of the proposed two detection schemes is to adjust the inaccurately estimated CCI strength by utilizing the CCI-correcting factors while avoiding high computational complexity,and subsequently remove the CCI strength from the victim cell by employing the post-compensation signal-processing technique.Simulation results demonstrate that the proposed VDDC and ADC detection schemes can effectively eliminate the CCI-induced errors with low computational complexity compared to the state-of-the-art detection schemes.