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On The Threshold Voltage Detection For Multi-level Cell NAND Flash Memory Channels

Posted on:2022-01-11Degree:MasterType:Thesis
Country:ChinaCandidate:C F LvFull Text:PDF
GTID:2518306734966269Subject:Computer system architecture
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With the development of storage technology and chip architecture,NAND flash memory has become one of main new digital storage systems due to its small size and large capacity.Multi-level cell(MLC)technology doubles the storage capacity of the flash memory,but it also brings stronger noises and unavoidable interferences,thus reducing the reliability of stored data.The use of error correction codes is an effective method to improve storage reliability.Low-density parity check(LDPC)codes and the iterative decoding methods based on soft information are widely used in NAND flash memory,because they usually have better error-correction capabilities than BCH codes and RS codes with hard-decision decoding.The soft information required for the decoding has a great impact on the decoding performance of LDPC codes.The more accurate the soft information is,the better the decoding performance becomes.The calculation of soft information depends on the detection of the stored data.In MLCNAND flash memory applications,the detection of the stored data is to detect the threshold voltage of the memory cell,which is often to sense a threshold voltage range.The smaller the voltage range is,the more accurate the obtained soft information is,but the higher the related computational complexity is and the greater the delay is.Therefore,how to detect effectively the threshold voltage of the memory cell for the MLC-NAND flash memory is a research direction worth exploring.This thesis studies the physical structure and characteristics of the MLC NAND flash memory,establishes the channel model of flash memory,analyzes the characteristics of the soft decision decoding of LDPC code in flash memory,and explores and designs the threshold voltage detection technology on MLC NAND flash memory cells according to the calculation requirements of soft information.The main contributions of this thesis include the following two aspects.(1)A non-uniform threshold voltage sensing optimization scheme based on the relative accuracy loss rate is proposed.Firstly,according to the physical structure and characteristics of MLC-NAND flash memory,combined with the Monte Carlo simulation,two main noise factors disturbed the threshold voltage of the memory cell,cell-to-cell interference(CCI)and retention noise(RN),are analyzed.Due to the complexity of the noises,it is very difficult to characterize exactly the threshold voltage of a memory cell.Secondly,using the Gaussian approximation method,a computable mathematical representation of the threshold voltage distribution of the memory cell is given.This approximation is validated by simulations.Thirdly,based on the calculation of the soft information(LLR)of the LDPC decoding under the MLC-NAND flash memory channel model,the concept of the relative precision loss(RPL)rate is presented and used to determine the overlapping region of the threshold voltage that causes the storage errors.Then,a non-uniform threshold voltage sensing optimization scheme is designed.Finally,simulations are carried to show the advantages of this proposed scheme in terms of storage reliability.(2)A low-latency read voltage optimization scheme based on the estimations of the mean shifts of neighboring states is proposed.Firstly,the delay problem caused by the rereading mechanism in NAND flash memory is introduced.In particular,the more the number of rereading is,the longer the delay is.The design of the optimal read voltages can decrease the number of rereads and then reduce the delay.Secondly,combined with the characteristics of CCI and RN,the shift of the mean of the threshold voltage distribution is estimated without knowing the threshold voltage distribution.Then the optimal read voltages are designed.It is worth mentioning that this design of the read voltage optimization requires only a one-step calculation and is a low-latency design.Thirdly,the effectiveness of this design is validated by the evaluation results of the optimal reading voltages obtained by the non-uniform threshold voltage sensing optimization scheme based on RPL proposed in this thesis.Finally,the performance of the optimized design of the read voltage is demonstrated through simulations.
Keywords/Search Tags:Multi-level cell (MLC) NAND flash memory, Low-density parity check (LDPC) code, threshold voltage detection, cell-to-cell interference, retention noise
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