Iterative Recovery Phase For Multi-level Cell NAND Flash Memory Systems

In recent years,Multi-Level Cell(MLC)technology has been proposed,which makes the NAND Flash storage density increased but make the system noise greater.The Intel-Cell-Interface(ICI)noise is one of the most serious noise.Low Density Parity Check(LDPC)code has increased a lot of latency in MLC NAND Flash.How to effectively reduce latency is a hot but difficult spot in current research.To solve the latency problems of LDPC codes applied in MLC NAND Flash,the optimization and redesign of the data recovery phase is proposed in this paper.The information of the threshold voltage mapping and decoding would be exchanged and iterated in this design.The proposed scheme,under the premise of not losing system performance,effectively reduce the latency by lowering the threshold voltage sensing levels(the main latency of the system).The main contents are divided into the following three parts:Firstly,for the ICI,the MLC NAND Flash mathematical model based on full-bit-line structure and multi-level programming strategy is built.Through rigorous and reasonable derivation,the log-likelihood Ratio(LLR)soft information is calculated,and the MLC NAND Flash mathematical model is improved.According to MLC NAND Flash mathematical model,the iterative data recovery phase scheme is proposed.Based on different conditions,such as different sensing levels and LDPC of different code rates,the new scheme is verified to be much better than the traditional scheme on the error correction performance.Meanwhile,the better error correction scheme can reduce latency by reducing sensing levels.The simulation results show that the new scheme using the 3-level sensing accuracy is better than the traditional scheme using 6-level sensing accuracy,which means the new scheme can solve the latency problem and at the same time,improve the system performance.Based on the MLC NAND Flash system,the Extrinsic Information Transfer(EXIT)algorithm is adjusted for the iterative data recovery phase scheme.And the performance of different error-correction code under the scheme is analyzed through the EXIT curve and simulation results.