Research On And Design Of High-speed Encryption And Decryption Of Network Messages Based On FPGA

With the rapid development of network technology,network data interaction has become more frequent and complex,and 10G Ethernet has also begun to be applied on a large scale.The upgrade of the network not only brings convenience to users,but also brings hidden dangers such as information leakage and theft,which threaten the security of network data.Therefore,in order to effectively protect user information in network communication,it is urgent to research and develop a high-speed encryption and decryption system for network messages.There are many ways to design and implement data security transmission,from simple and low-cost microcontroller design,to more complex embedded software design,to field-enabled FPGA design based on hardware description language,all of which can realize the function of data protection.The FPGA design scheme has unique advantages in the design and implementation of Ethernet network security due to its characteristics of parallelization,flexible design and reprogrammability.Therefore,based on the FPGA development platform,this thesis studied the network packet processing method related to the 10G Ethernet protocol and the AES algorithm to protect the network packet.Based on the research of related technologies,this thesis used verilog to design a high-speed encryption and decryption system for network packets.The transmitter of the system extracted the plaintext sequence from the message for data encryption,replaced the original data with the encrypted ciphertext,and then transmitted the generated Ethernet message.The receiver of the system recognized the 10G Ethernet network message,and then completed the decryption work to obtain plaintext data.The main research contents and results of this thesis are as follows:(1)Aiming at the protocol processing of 10G Ethernet packets,the optimized flow of the system transmitting and receiving packets was designed,and the encrypted packets were checked by using the hybrid parallel connection CRC algorithm to complete the generation of Ethernet format packets.(2)In order to enhance the flexibility of the system,this thesis designed a multi-queue data processing mode for the needs of multi-users,and completed the configuration of multi-queue parameters through the system control module.The scheduling and flow control module was designed to complete the independent and fine throughput control of each queue.The timedivision multiplexing design mode was adopted to complete the processing of multi-queue data,which improved the flexibility of the system while only adding a small amount of logic resources.(3)Aiming at the AES encryption and decryption in the 10G Ethernet protocol,this thesis adopted the CTR grouping mode for AES to solve the problem of increased packet length during encryption and decryption of Ethernet packets.The optimized pipeline process was designed to increase the AES data throughput and enabled it to support high-speed network packets.Finally,Modelsim software was used to build a simulation platform to simulate and verify the system and compiled and designed the FPGA.The experimental results prove that the system designed in this thesis can stably complete the encryption and decryption of 10G Ethernet network packets,and provides an effective solution for solving the information security problems of highspeed network packets.