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Design And Implementation Of Gigabit Ethernet Adapter Based On SOPC

Posted on:2009-12-04Degree:MasterType:Thesis
Country:ChinaCandidate:L ChenFull Text:PDF
GTID:2178360278964288Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Gigabit Ethernet in Object-based Storage Systems provides high performance, low cost and extensible interconnection. Implementating Gigabit Ethernet adapters in the SOPC (System On Progammable Chip) method can effectively utilize the advantages of SOPC, such as the customization of software/hardware and the system extensibility, and sastify the requirement of Object-based Storage Systems.The research on the architecture and work principle of the Gigabit Ethernet adapter is based on the analysis of Gigabit Ethernet IEEE 802.3z protocol. The Gigabit Ethernet adapeter is implemented in the FPGA (Field Programmable Gate Array) device by adopting the SOPC method. The interface logic of GEMAC (Gigabit Ethernet Media Access Control) is designed and implemented.The design of the Gemac interface logic uses the Verilog hardware description language and achieves all functions of the MAC layer. The standard 1.25 Gbps Gigabit Ethernet applications, the point-to-point topology and the fabric topology are supported. The serial high-speed bit-stream transceiver is realized. The MAC layer achieves the sending and receiving of the Ethernet frame and the duplex flow control. The frame sending engine sends the data delivered by the upper layer in the Ethernet frame. The frame receiving engine handles the frame destination errors, the frame checkout errors and so on when receiving frames. By the identification and control of the Pause frame, the flow control module achieves the end-to-end flow control. Via the Avalon bus interface, the GEMAC interface logic is connected with the Scatter-Gather DMA module, which accesses DDR SDRAM effectively.In order to improve the system performance, the coding in hardware description language, the logic synthesis, place and route, the timing constraint are optimized from the perspective of resource and timing. A system-level platform is built to complete the functional validation and performance evaluation of the Gigabit Ethernet adapter.
Keywords/Search Tags:Gigabit Ethernet, Adapter, Field Programmable Gate Array, System On Programmable Chip
PDF Full Text Request
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