Research And Design Of Multi-Standard Multi-Level Programmable I/O Interface

As semiconductor technology has evolved,smaller feature size allows manufacturers to integrate more units on each chip,and the chip integration level has reached millions of doors or even tens of millions of doors.For Application Specific Integrated Circuit(ASIC),the design difficulty and manufacturing cost have increased significantly.However,the increase in chip integration makes the computing power and the processing capacity of semi-custom Field Programmable Gate Array(FPGA)is getting stronger and stronger.On the other hand,the semi-custom FPGA development cycle is shorter and the product risk is lower.In engineering applications,through programming development and cooperating with other circuit modules,it is possible to build a complex electronic system to process various types of data.It shows that FPGA has better application compatibility and flexibility.Nowadays,With the rapid development of information technology today,more and more application scenarios such as high-end processors,5G networks,and aerospace need to process massive amounts of data in real time.Meanwhile,FPGA is suitable for occasions with high requirements on throughput and transmission speed.As an important communication module between FPGA and the outside of the chip,the general I/O interface of FPGA must be able to adapt to the application needs of different voltage and the increasing transmission speed.So general I/O interface is mainly composed of two parts: input and output buffers and input and output logic resources.The input and output buffers are directly facing the outside of the chip,can be programmed to support multiple voltage standards.At the same time,it should have a good transmission rate.According to Moore's Law,the feature size of the chip is reduced,and the power supply voltage is also continuously reduced.In the case of using a lower power supply voltage,the general I/O interface must not only maintain sufficient transmission speed and high performance,but also cover a high range of voltages.But the traditional general interface design method is difficult to cover the two different situations of high performance and high range.In order to solve this problem,we consider designing two types of input and output buffers,one is a high-performance input and output buffer,using 1.8 V low-voltage devices ensure the operation speed of the circuit,but only support voltage standards below 1.8V;the other is a wide-range input and output buffer,which supports 1.2V-3.3V voltage standards.Since 1.8V devices are also used,how to make all transistors withstand voltage higher than1.8V is the focus of the design.This paper focuses on the high range of input and output buffers,and classifies 37 different I/O standards with a working voltage range of 1.2V-3.3V.Multiplexing input and output buffers to save circuit area,5 input buffers and two output buffers are finally designed.In order to make the voltage at both ends of the transistor not exceed 1.8V,a withstand voltage design is added to the circuit modules directly driven by the power supply voltage.There are other important circuit modules,including: fully differential output bias generation module,overvoltage protection module,low power consumption design,etc.After completing the circuit design,the layout was drawn and the circuit was simulated based on the layout.Finally,the FPGA general I/O interface designed in this paper is taped out under 28 nm CMOS technology.The test results show that the circuit has complete functions,performance indicators can meet the indicator requirements,and the maximum transmission rate can reach 1Gbps.