Design And Optimization Of High Performance Processor Security Module

Information security is the main theme of today's era.In the field of information security,the United States has always been in the leading position and the monopoly position of IP intellectual property of integrated circuits.After the incidents of"ZTE"and"HUAWEI"in2018,2019 and 2020,the world once again paid attention to the information security field such as chip processor.As the university of California,Berkeley,open source of RISC-V instruction,a lower threshold of reduced instruction set of CPU design,is bound to widely used in the field of 5G high-speed communication,AI(artificial intelligence),industrial robots,IOT(Internet of things),intelligent automation,and even national defense and other fields.Thus the processor security issues can also cause the urgent attention of the customer.Currently in security encryption algorithm is the main way of the software and hardware,because the software is restricted by equipment and is not stable,affect the quality of data transmission,therefore the design through the special chip to realize the hardware algorithm is a mainstream in the field of information security,which is easy to embed,easy to perform complex function,IP reuse is strong,high reliability,high rate of encryption and lower overall cost.In this paper,at first,based on the study of the mathematical priciple of AES and the principle of Rijndael algorithm.The RTL's implementation of AES and encapsulated it into the IP soft core was in the Modelsim,VIVADO 2015.4/2018.3 environment.The consumption of programmable logic resources(Slice LUTs)of both structures,the loop iteration structure and pipeline structure,was through the sequential synthesis and layout.The IP's interface has been designed and optimized,which was based on the AXI4/AXI4-Lite protocol standardization.The parameters such as maximum clock frequency and area of two hardware structures are obtained by using Synopsys's DC synthesis in the library of tt28nm,TSMC.Next,the IP was integrated on BOOM processor,based on risc-v ISA,university of California,Berkeley,and the driver was finally be completed.By using Synopsys's DC in the library of tt28nm(TSMC)could obtain the maximum clock frequency was 1.92 GHz,the area was 0.0188)8)~2(the loop iteration structure).By using the same method could obtain the pipeline structure AES's maximum clock frequency was 2.56GHz,the area was0.178)8)~2(Based on the current two structures of AES and BOOM processors have not been asynchronous processing,so the throughput and other performance parameters are calculated with the DC comprehensive value of BOOM processor,which was 1.13GHz).The joint debugging was realized by integrating the UART 16550 IP,which could print the encryption/decryption information of AES on the PC monitor.The horizontal and vertical comparison of various performance parameters between the two AES hardware structures and ohers in reference was completed.Finally in Xilinx Virtex-7 XC7VX690T-2 ffg1761c FPGA platform completed AES IP integration of loop iteration and pipeline structure,completed function test and board-level verification,and it is concluded that the structure of the loop iteration AES unit's consumption was 3071 Slices,interface unit's consumption was 307 Slices.By running a large number of test vectors at the board level,it was calculated that the peak throughput was 1.12 Gbps,encryption efficiency was 0.37 Mbps/Slice;The pipelined AES consumed8023 Slices and its interface consumed 353 Slice.The peak throughput was 144.14Gbps and the encryption efficiency was 18.40Mbps/Slice.This research has significantly improved the security performance of current BOOM processors,especially in terms of encryption throughput and encryption efficiency.