| The solution to the low power consumption of security chips in the fields of the Internet of Things,smart home,portable devices,etc.is the constant pursuit of all technology developers.Therefore,this paper proposes a new peripheral serial transmission bus scheme applied in information security system on chip（So C）to achieve the design goals to achieve ultra-low-power communication,increase communication rates,conserve interface resources,and reduce chip area.One-Wire Bus is a peripheral serial expansion bus technology.Only a single signal line can realize the communication function of transmitting clock and data and supporting half-duplex.The device in slave mode implements the parasitic power function.This paper applies the bus technology to the ultra-low-power So C chip,and further optimizes and improves its interface function,so that the final interface controller has higher compatibility,lower communication power consumption and greatly improves the communication performance of the interface.This paper focuses on the implementation process of the One-Wire bus interface controller in the ultra-low power So C.Firstly,the importance of realizing low power consumption design is introduced and the current bus technologies that can realize parasitic power supply function at home and abroad are compared.Secondly,it introduces the characteristics of One-Wire bus parasitic power supply and analyzes the advantages and disadvantages of several ways of using the same cable to communicate power and data,and analyzes the specifications of the One-Wire protocol in detail.Then,the realization scheme of using Verilog HDL to complete the RTL level design of the interface controller is described.Subsequently,the process of RTL-level verification,Post＿Layout-level verification,Field Programmable Gate Array（FPGA）verification and testing of each function of the design module is clarified.This design is based on the HW＿Embedded NORD Flash Low Power process,and the chip area is about 1000μm×1000μm.The final verification and test results show that the One-Wire bus interface controller designed in this paper can achieve the expected functions.The contributions of this paper are as follows:In order to improve the compatibility and portability of the function of the One-Wire bus interface controller and make the application environment of the chip more flexible,the design of this paper adds the hardware logic circuit of the master function.The implementation of this function can control the circuit more conveniently and efficiently and reduce the dynamic power consumption of the master device;considering the realization of testability design to perform structural testing of the chip,in order to avoid the scan chain data triggering the pull-up and down signals and enable signals in the One-Wire interface PAD during serial shifting,the chip will appear in a metastable state caused by the transition delay time during the structural test,which affects the accuracy of the structural test results.The design scheme of pattern shielding technology prevents the interference of the structural test to the internal signal of the PAD,and improves the accuracy of the chip test.In order to reduce the dynamic power consumption of the One-Wire bus interface controller and the So C,the self-detecting communication status function has been added to the interface design.If there is no communication within a period of time after the interface communication function is turned on,the chip will automatically enter the low-power sleep mode,and can automatically wake up the low-power state through IO.The design can flexibly control the working state of the chip,so that the power consumption of the chip can be further reduced;at the same time,in order to reduce the dynamic power consumption of the So C and improve the One-Wire bus interface controller’s ability to carry data and the compatibility of the interface function.The One-Wire bus interface controller designed in this paper adds the access interface to the dedicated RAM,which avoids continuous access to the CPU when the data of the algorithm module is carried,which improves the flexibility of data transmission while reducing the operating frequency of the CPU.The test of the finished product shows that if this function is turned on,the total power consumption of the chip can be reduced by about 20%. |
