Research On Technology Of Low Power Test Schedule Based On Network On Chip

With the ever increasing of integration and complexity of the integrated circuits,especially the development of SoC (System-on-Chip) and NoC (Network-on-Chip), chips testing confront of more and more challenges. Power, data volume and test application time are among the most challenging problems. However, with technology development and the widespread use of a variety of high-performance and portable devices, power problems of electronic equipment have become increasingly prominent, and it has become an important aspect which design and test must focus on. A good performance of the system will not only depend on low-power design techniques, but also on the use of low-power constrained testing technology.The rasing of multi-core chip test data volume results in a sharp increase in test power consumption. Therefore, the study of multi-core chip low-power BIST test pattern generation and application is of great significance. NoC is the new paradigm in core-based system design. Reuse of the on-chip communication network for NoC test is critical to reduce test cost. However, efficient reuse of the communication network for test of legacy cores is challenging. We propose a low-power test schedule method, for every schedule port we prefer to schedule the core with lowest power, so every core is scheduled in its lowest power, resulting lowest total power.In this dissertation, the BIST-based multi-core low-power test pattern generation architecture is researched, at the same time, low-power multi-core test access mechanism TAM (Test Access Mechanism) and the control circuit sharing strategy are investigated. We examine how to transform the multi-core chip BIST test scheduling problem model into more than one constraint, especially power constrained resource optimization problem and we solve the problem of test power, test time and area overhead comprehensively through scheduling algorithms. A power optimized test scheduling method is proposed, which considers both test time and test power factor. This method reduces the total test power substantially by reducing the communication power. Experimental results for the ITC'02 benchmarks show the effectiveness the new methods.