Low Power Design Flow Of CPU Module In 7nm Process

Driven by Moore's Law,IC technology continues to develop rapidly.Area and timing are no longer the only indexes to be considered in IC design.Power consumption has gradually become an important factor restricting the development of IC.With the development of transistor size from micron to nanometer,the integration of chip shows exponential growth,and the static power consumption can not be ignored.In the case of extremely small size and high integration,how to balance timing and area to reduce power consumption has become a major challenge in all stages of chip design.Based on TSMC 7nm process,this paper takes ARM CPU core module ananke?core as the research object.With the help of Cadence Genus and Innovus,the low-power technology is used to complete the flow design of the module from RTL level to back-end layout and wiring.At the same time,i Spatial technology and power optimization mode are used to optimize the logic synthesis and the back-end global physical synthesis process to further reduce the total power consumption of the module.The main content and research results of this paper are as follows:(1)Complete the low-power flow design of the ananke?core module from RTL level to back-end placement and routing.Under the definition of UPF,on the premise of improving Power consumption,Performance and Area(PPA),with the help of Genus,we have completed the transformation from RTL level to gate level netlist.With the help of Innovus,we have realized the floorplan,placement,clock tree synthesis and routing of each unit in CPU module.We have also repaired and optimized the problems of timing violation,high power consumption and high area utilization in the process of physical design.(2)The front-end RTL level logical synthesis behavior is optimized based on i Spatial solution.Use Genus tool to reconfigure the front-end logic integration process and import data of ananke?core module.Based on the concept of engine unification,call the Giga Place and Giga Opt engines of Innovus tool.In the frontend logic synthesis stage,the quick placement and routing between units,timing violation,power consumption and other indicators are repaired and optimized to realize the advance prediction of PPA results of back-end design.The logical structure optimization based on the accurate layout results of the front end not only reduces the iteration times of the front and back ends,but also improves the quality of the gate level netlist synthesized.The running time of the back-end layout process is saved about 4 hours,the power consumption is reduced by 1.21%,and the timing optimization is 67.21%.(3)A new power optimization process is introduced to intervene the optimization behavior in the global physical synthesis stage and further optimize the total power.On the basis of the original process,this design adopts the highintensity power consumption optimization mode,and introduces the Force Downsizing behavior to replace the unit with unchanged function and smaller area to achieve a significant reduction in power consumption.Then the Timing sequence repair considering Power consumption is carried out through the Power Aware Timing Opt process.Finally,the Aggressive Power Reclaim step was introduced to carry out the secondary reduction of total Power consumption under the condition of meeting the timing constraints.Meanwhile,according to the proportion of dynamic and static power consumption in the module,the leakage To Dynamic Ratio parameter is set to 0.1,and the dynamic power consumption is optimized.As a result,the total power consumption of the module is reduced by 6.35%,the area utilization ratio is reduced by 3.17%,and the timing sequence is optimized by36.65%.In this paper,i Spatial solution and power optimization in back-end physical design provide theoretical basis and solution for power optimization from RTL level to back-end layout and wiring stage in chip design,which has certain reference significance on how to reduce chip power.