Power Consumption Optimization Of Contactless Smart Card Design

Contactless smart card is favored by the majority of users for its high reliability,easy operation and other adventages, and has been used in public transportation,health care, access control and other fields. Because it’s without power, the smart cardneeds to get energy from the reader through antennas to complete the transaction,which poses a challenge to its power consumption. Excessive power consumptionwould lead to IR Drop, large current density, EM(Electronic Migration) and otherissues, meanwhile the rising temperature caused by the power consumption wouldaffect the performance, delay of the devices and the interconnect wires, then directlyimpact the function and stability of the chip. So it has become increasingly necessaryto optimize the power consumption in the design.This thesis firstly completes a detailed analysis of the static and dynamic powerdefinition, and proposes solutions to the problems of IR Drop and EM brought byhigh power consumption. Then, from the view of contactless smartcard chip ofback-end design, based on Synopsys’ digital design platform and a comprehensivepower analysis, it optimizes the power at the extreme mainly from the following threeaspects of the logic design, floorplan and clock network design. In the logic designphase, adjust the compilation strategy and design constraints according to thecharacteristics of the chip modules, and present the incremental compilation to thechip based on the signal average toggle rate at normal condition. At the floorplandesign stage, introduce the average and real-time power consumption of the chip,design the floorplan and power mesh in term of current consumption of each moduleaiming at maximum optimization of IR Drop and current density. In the clock networkdesign phase, bring in an XOR self-gating techniques that based on the value of theregisters, in considering the parameters of chip area, power consumption and clocksignal, through iteratively attempting to use different design parameters, choose theclock inverter to build the chip clock network by the bottom-up method.After finishing the whole back-end design flow, the timing, utilization and otherparameters remain basically the same with the last version to ensure design continuity.And complete all the verifications of the chip to guarantee the correctness of thedesign. Comparing with the last version, the new design has reduced the total powerconsumption of38.4%, the voltage drop and ground bounce have been reduced by40.1%and30.5%, the current density of power lines and signal lines have beenreduced by4.6%and20%separately. The results show that the thesis successfullycompletes the power optimization of the contactless smart card without affecting thechip’s function. To summarize the successful optimization process on the contactless smart carddesign, the thesis puts forward a back-end design flow of optimization based on acomprehensive power analysis. Or more specifically, during the design, take theanalysis results of power information, IR Drop and EM at all stages into considerationto optimize the power consumption, and gradually get the optimum results in theprocess of continuous iterations, which is useful and meaningful for power optimztionin the future chip design.