Research And Design Of Information Security SOC Based On RISC-V And Cryptographic Coprocessor

With the rapid development of the Internet of things and the Industrial Internet of things,the problem of information security of Internet of things equipment has attracted more and more attention.To ensure the confidentiality of data transmission on these Io T devices and better meet the requirements of low delay in application scenarios,On the basis of the open-source Hummingbird E203 MCU(micro control unit),a coprocessor suitable for AES(Advanced Encryption Standard)and RSA composite encryption scenarios is expanded to design a RISC-V SOC with extended security scenarios by extension instructions.To meet the low-cost requirement of Io T chips,the AES,RSA algorithm core architecture is designed for low overhead.The AES algorithm core applies a structure of generating round-key in real time and Sbox is implemented by pure combinatorial logic.Compared with the one-time roundkey generation scheme,the chip area is reduced by 22.5%.The RSA algorithm core divides long integer addition into several 32-bit short integer additions.To solve the long integer carry bit problem in the Montgomery algorithm,a pulsating array structure is introduced,which effectively reduces the critical path delay.This paper not only verifies the function of the coprocessor core on the FPGA development board,but also makes a detailed ASIC design,including detailed testability design and physical design.The AES algorithm core designed in this paper has been successfully tape-out under SMIC 180 nm process.The designed coprocessor core has been made a detailed testability design based on the TSMC 12-nm process,and a detailed physical design and performance evaluation based on Huahong 40 nm process library.The area of AES core after synthesis is 30805 square microns,the hardcore area after the physical design is 44944 square microns,and the throughput can reach 3.3Gbps.The area of RSA core after synthesis is 94552 square microns,and the area after the physical design is 129600 square microns.1024-bit RSA operation can be carried out 48 times in one second.The SOC is implemented and tested on the Xilinx FPGA development board with the test programs that call and do not call coprocessor.The operating speeds of AES 128-bit under the co-processor support have increased by more than 234.43 times compared with implementation without extension instructions,and the RSA1024-bit operation speed is increased by 239.91 times.