ASIC Implementation Technology Of High-Speed DSP Algorithms

It is necessary to seek the implementation approach of algorithm with specific hardware to fulfill the request for high speed and cosmically capability in DSP system, while, the design efficiency for the tradition ASIC is on the low side and the design cost is on the high side, as severely restrict the implementation study and application for DSP algorithm in ASIC. The hierarchy design idea being put forward, HDL language being introduced and FPGA (the important embranchment of ASIC) advancement make the problem a good solution.The function of FPGA is not only that it simply integrates some IC in miniature and being the cheap substitute of ASIC, but also that it is very suitable to design, debug, analyze, and verify some hardware algorithms with its field programmable capability and offer the appropriate implement platform. In the future, the general DSP processors will dominate the complex algorithms field (for example, those with multiple if-then-else structures), while, the specific processor based on the FPGA will reign the algorithms in many sensor application, such as MAC, FIR, FFT, and so on. As a result, studying implementation technology with hardware for some algorithms is very important to improve the specific processor and set up the high speed DSP system.This paper lays emphasis on studying the hardware implementation structure for some DSP algorithms, optimizing the design, and analyzing the performance and verifying the result. Based on the studying for the implementation of DSP elementary algorithms, we study and analyze the implementation structure for three class algorithms, convolution, FIR and rank order filter, and accomplish the optimization design for the two algorithms. Finally, we analyze a factual DSP system algorithm (LMS), design the implementation structure and verify the performance of the involved algorithms.