Design On Key Circuits Of Vector Modulator In CMOS Integrated Circuits

In modern mobile communication systems,traditional analog modulation is difficult to meet the requirements of such high-speed communication.At present,the mainstream digital quadrature modulation generally divides the baseband signal into two mutually orthogonal I and Q signals,which can improve the communication rate.In order to achieve higher transmission rate and large capacity,higher-order digital modulation is often used,which requires higher symbol rate,so phase modulation and amplitude modulation need higher accuracy.The method of digital quadrature modulation depends on the digital to analog converter(DAC)to convert the digital baseband signal into analog signal.At the same time,the baseband output is generally a high-speed serial control signal.Therefore,it is necessary to convert the high-speed serial data into the parallel control signal recognized by the DAC.Because the digital to analog converter needs to have high speed,precision and output dynamic range in the process of realizing vector modulation,it puts forward great requirements for the design of DAC itself and the input interface speed of DAC.Focusing on the two key circuits of the above vector modulator,namely DAC and high-speed interface,after studying the structure of high-speed and high-precision digital to analog converter and the design principle of high-speed serial communication interface,a 12 bit current-steering segmented DAC with integrated high-speed interface and built-in bandgap reference is designed and verified on MPW with an overall area of660?m×880?m based on HHGrace 110 nm 1P5M CMOS process.The main work and contributions of this thesis are as follows:1)The advantages and disadvantages of different DAC architectures and segment selection are compared.The effects of output impedance,random mismatch,system mismatch and noise on DAC performance are analyzed,and the MATLAB modeling is analyzed.With a 4+3+5 segmented structure,the DAC achieves differential nonlinearity(DNL)below 0.08 LSB,product nonlinearity(INL)below 0.35 LSB,spurious free dynamic range(SFDR)greater than 72 d B in the Nyquist domain at a sampling rate of 50Msps,and the core area of the chip is 0.1mm~2.2)A high-speed LVDS receiving interface is designed.The high-speed LVDS interface is used to receive the high-speed serial data stream,and the low-voltage differential signal is converted to the standard level of compatible digital unit.When the input signal is 2 GHz,different input common mode interference,differential mode attenuation and different process angles are simulated.In the worst environment,it can still output better waveform to complete data reception and level conversion.3)To provide control input for DAC,a 600 Mbps high-speed deserializer and decoding circuit in DAC are realized by digital logic synthesis.The clock tree is constructed by automatic layout and wiring to ensure the normal timing network and reduce the power consumption,area,design complexity and design cycle of digital circuit.