The Research And Design Of A New High Speed And High Resolution Dual Slope ADC

Due to the proliferation of sensors in the market, low-power and high-precision sensor readout circuits have become more demanded in the recent years. These sensor readout circuits in turn require ADC that exhibits low-power and high-precision characteristics. Therefore, sigma-delta ADC, SAR ADC and integrating ADC are better choice for implementing sensor readout circuits. Sigma-Delta ADC has the advantage of high resolution, but the backend digital filtering circuit requires large chip area. SAR ADC can operate at high conversion speed, but it has the inaccuracy problem of matching wide range of capacitor values, which makes it difficult to achieve high resolution. Comparatively, integrating ADC has the advantage of high resolution, low power consumption and simple structure. Moreover, dual-slope integrating ADC is invariant to the mismatch of capacitor and resistance. Nevertheless, it suffers from long conversion time and it need large capacitor, which is not cost-effective to be integrated. In addition, the offset of the integrator op amp in dual-slope integrating ADC is also another important factor affecting conversion accuracy and code consistency.This thesis proposes an improved ADC architecture combining dual-slope integrating ADC and SAR ADC. It not only shortens the conversion time tremendously and lowers the value of the integrating capacitor enabling it to be integrated in the integrating ADC, but it is also able to solve the inaccuracy problem of matching wide range of capacitor values in SAR ADC. In addition, the thesis adopts chopper-stabilization technique in a proposed fully differential integrating architecture to eliminate the integrator op amp offset problem. Using standard 0.5μm CMOS technology, for a sampling frequency of 2 kHz and an input signal frequency of 500 Hz, the simulation results show that an ENOB of at least 16 bits, a total power consumption of 4.5mW at 5V supply, and a SFDR of 105 dB are achieved.