Hardware Architecture Design For Narrowband IoT Chip Multimode Accelerator

In recent years,the rapid development of Internet of Things technology is widely regarded as another major change in the global information industry after Internet technology.In the context of the current Internet of Things protocol standards with multiple choices,a chip compatible with multi-mode protocols is an important way for networking technology to land.At present,there are relatively few domestic research results on narrowband IoT chips compatible with multi-mode protocols.In this context,this paper designs and implements a multi-protocol fusion narrowband IoT chip based on the national key research and development plan Narrowband IoT chip multi-mode accelerator compatible with NB-IoT/BLE/GPS multi-mode protocol,the specific work is as follows:Firstly,the technical standards of the NB-IoT/BLE/GPS multi-mode protocol are deeply studied,and the similar functions in the digital signal processing method are analyzed.It is proposed that both channel decoding and FFT are involved in the multi-mode protocol,and there are compatible and possible application scenarios,and the realization possibility and application value of multi-mode accelerators are confirmed by analyzing their specific technical indicators.Secondly,based on the list Viterbi decoding algorithm,a multi-mode Viterbi decoding that can be applied to(3,1,7)tail-biting convolutional codes and(2,1,4)convolutional codes is designed and implemented.It is compatible with the channel decoding scenario under the NB-IoT/BLE dual-mode protocol,and has a performance improvement of 0.2?0.5d B compared to the traditional Viterbi decoder.In addition,the implementation architecture of parallel decoding and serial checking is used,and the decoder is triple-folded to reduce hardware resource consumption on the basis of satisfying the module throughput rate.Thirdly,a FFT accelerator based on memory architecture for parallel computing of16-point data is designed and implemented,which supports 32-2048 points and is compatible with time-frequency conversion and signal synchronization scenarios under the NB-IoT/GPS dual-mode protocol.A radix-2/radix-4 hybrid FFT algorithm is used,which improves the calculation speed by 40%?50% compared with the radix-2algorithm.In addition,a conflict-free addressing scheme for FFT data is designed,which realizes the conflict-free addressing and conflict-free access of 16-point parallel data to the ping-pong memory bank.Finally,the ASIC implementation of the multi-mode accelerator is completed,and the implementation results and related analysis of the top-level architecture,multiplexing method,module throughput rate,and logic synthesis result is given.In addition,functional verification of the multi-mode accelerator has been completed by using the FPGA platform.The research results of this paper can provide a certain theoretical reference for the research of multi-mode narrowband IoT chip design,multi-mode list Viterbi decoder,and reconfigurable FFT accelerator.