Signal Integrity Analysis In High-speed Interconnect Design

With the rapid development of high-speed digital circuit and high-integrated chip technology, signal integrity issues become increasingly more and more serious. These problems have brought great challenges to the design of system hardware. High-speed interconnect system design have to face Reflection, Crosstalk, False trigger, Damping oscillation, as well as Propagation delay and other signal integrity issues. The success to the high-speed interconncetion system design lies on whether we can cope well with the signal integrity issues caused by high-speed signal interconnects. So it is extremely important that the structure of high-speed interconnect is modeled and simulated fast, accurately and efficiently. This paper has made a theoretical research and practical simulation to high-speed interconnect design for the signal integrity issues.Firstly, basing on the explanation of the transmission line model, the formation of reflection and crosstalk mechanism are analyzed in detail. And interconnect parameters to disturb the level of crosstalk voltage are compared. According to the simulation results, this paper draw the best solution in order to optimize the design object. And then it conducted a detailed theoretical analysis to characteristics of the differential transmission line and simulated signal integrity performance.Secondly, various discontinuities in high-speed interconnects have been analyzed and simulated on signal integrity, such as: corner, via, and imperfect reference planes. The analysis is mainly based on the combination of 3D full-wave electromagnetic and high-frequency circuit simulation in frequency and time domain. Therefore all kinds of operation behavior are understood which high-speed signal propagation along the discontinuities in Single-Ended and Differential interconnects. So we could draw some conclusions which can reduce SI issues through simulation and analysis.Finally, it studied the basic timing equation for common-clock and synchronous circuit architecture in the high-speed interconnect system. At the same time, it also combined with a design of embeded system to make a simulating analysis on the key network part, to verify the constraints condition on timing.