A Near-threshold Timing Error-tolerant Circuit And Application In Processor

With the expansion of IoT applications,energy efficiency has become an important indicator of integrated circuits.The near threshold calculation is an effective way to improve the chip energy efficiency.The timing characteristics of the circuit at near threshold voltage are extremely sensitive to the process,voltage,and temperature(PVT)variation.In the traditional integrated circuit design method,the loss of performance,area and energy will be caused by adding timing margin,and the influence is more obvious at near-threshold voltage.In order to reduce timing margin in the design,timing error detection and correction(EDAC)techniques have been widely studied.In the traditional EDAC circuits,on the one hand,the implementation of timing error detection needs to add a large number of transistors on the basis of the structure of the traditional register(or latch),which leads to the increased area of the timing error-tolerant circuit and even the whole system.On the other hand,the correction of timing errors often leads to additional performance overhead.With the increase of timing error rate,the performance of the system will decrease significantly.In this paper,the area and performance overhead of traditional EDAC circuits are studied deeply.A low-power timing error-tolerant register with in-situ correction(ESCFF,error in-situ correction flip-flop)is designed.It is applied to the domestic self-designed commercial processor CK802 under the condition of near threshold.The specific contents and innovations of the work are as follows:1.In order to solve the problem that the traditional EDAC timing error recovery method leads to a significant loss of system performance and timing error tolerant circuits bring large resource overhead,a low-power timing error-tolerant register with in-situ correction(ESCFF)is designed:1)ESCFF adds 10 transistors to the traditional register.The timing error information is obtained by detecting the difference between the internal node of the main latch and the input signal through the improved flip detection method.2)ESCFF adds 4 transistors to the main latch logic.The working state of the main latch is directly controlled by using the timing error signal,and the in-situ timing error correction is completed by timing borrowing.2.In this paper,a low power timing error tolerant processor based on ESCFF is designed to verify the advantages of ESCFF error tolerant circuits in area and energy efficiency.Based on SMIC 40nm process,ESCFF is applied to domestic self-designed commercial processor CK802.The error recovery hardware structure of the system uses the method of global clock gating to compensate the error correction timing Under the condition of typical process,0.6V,25?;the point of first failure(PoFF)of the error-tolerant processor is 20.6MHz.The ESCFF register replacement rate is 10.38%.The total area of the standard cell is 9.74%larger than that of the processor without error-tolerant function.Compared with the fault-tolerant processor based on Razor-Lite,the additional area overhead is reduced by 4.5%.The simulation results show that compared with the reference design without error tolerant function,the energy consumption is saved by 47.5%and performance is improved by 16.7%at voltage of 0.6V.Compared with the EDAC techniques based Razor-Lite,the area cost is reduced by 4.5%and energy efficiency is improved by 10.6%.