Design Of14-bit SAR ADC With Self-calibration

As the design pursuit of industrial control system to the higher speed, lowerpower consumption, higher reliability, more precise, size scaling, peopleincreasingly pay attention to the main components of the system. Nowadays, themain ADCs in the market contains Flash ADC, SAR (Successive ApproximationRegister)ADC, Time-interleaved ADC、pipeline ADC and so on. While SAR ADCis widely used for its medium speed(<5Msps),medium precision(8~18bit),lowpowerful consumption and small size.According to the influences of system technology limit, including offset，noiseand so on, the resolution of traditional SAR ADC is limited to12bit. The design inthe paper is a14bit SAR ADC with the self-calibration DAC capacity array whichapparently improves the problem that high bit SAR ADC precision with lowaccuracy. Its power supply is1.8V with a125kHz clock signal and530Wpowerful consumption.The article introduces the background and purpose of the subject, thedevelopment trend of recent ADC, elaborates the situations between currentdomestic and international, and comparative analysis. The design is carried outunder the experimental conditions of smic0.18μm. The paper introduces thestructure of14bit SAR ADC, including digital part and analog circuit part. Firstly,the analog part consists of sample buffer amplifier, comparator, DAC capacity net(RDAC+CDAC+Cali-DAC), bias circuit and so on. Secondly, the paper shows thefunction, the key technology and simulation results of every part respectively. Toanalysis the reason of capacitor mismatch that reduces the resolution of ADC, and itintroduces the self-calibration algorithm based on a binary-weighted capacitivearray in mixed DAC. The basic idea of self-calibration is to add the self-calibrationoutput that getting from the self-calibration process to the conversion process ofCDAC through cushiony capacitors. The paper uses a uniform way to verify thecorrectness of self-calibration design through comparing the results of14bit SARADC without capacitive mismatch and self-calibration,14bit SAR ADC withcapacitive mismatch only,14bit SAR ADC with both capacitive mismatch andself-calibration. Thirdly, it states the implementation of Cali-CDAC array structurewith self-calibration.Finally, the paper uses TSMC0.18m COMS technology to design the keymodule layout of total circuit, including the design digital layout encounter and analog layout, then does the DRC and LVS verification. At last to verify thecorrectness of the design through back simulation for the whole layout.