Design Of Image Acquisition And Processing System Based On FPGA

Digital image processing technology is a research hotspot in today's society,and edge detection is a key step in digital image processing,which is widely used in mechanical vision,crack detection,video surveillance and other field.Therefore,a set of integrated image acquisition and processing system has a great application prospect.Traditional software serial image processing algorithm is inefficient and difficult to meet the real-time requirements.FPGA has the advantages of low power consumption,strong parallel processing ability and high speed,which can easily process the images collected by the camera in real time.Therefore,it has a very large application scene in the application system of image processing and high-speed computing.his design proposes an image acquisition and processing system based on CMOS camera + FPGA + SDRAM memory + serial port.Through the serial port,the Sobel edge detection based on FPGA is combined with the host computer to control the size of the edge detection area and adjust the edge detection threshold.The work contents are as follows:(1)Ep4ce15f23c8 of cyclone IV series is used as the main control chip to design the image acquisition and processing.Firstly,the register configuration of the camera ov7670 is completed through the SCCB interface,and the image collected by the camera is processed by graying,Gaussian filtering,Sebel edge detection and so on.(2)According to the working principle of SDRAM,the state machine is used to design its controller.Combined with ping-pong operation and asynchronous FIFO,the problem of cross clock and rate mismatch is solved,and the image storage module is designed.(3)According to the principle of VGA display,the design of VGA driver module is completed,and the result of edge detection can be displayed on the display screen in real time.(4)The communication module between serial port and FPGA is designed to complete the design of communication between host computer and FPGA.The host computer sends instructions to FPGA,and FPGA parses the received instructions to complete the corresponding functions.