Research And Design Of PAM4 High Speed Serial Receiving Equalizer

With the continuous advancement of communication technology,people’s demand for transmission rate is also gradually increasing.Four pulse amplitude modulation(PAM4)signal,as a new type of modulation,has a higher transmission rate and better frequency band utilization than the traditional non-return-to-zero(NRZ)signal.Therefore,PAM4 signals are widely used in high-speed transmission fields,such as optical fiber communications,data centers,and 5G communications.However,PAM4 signals also face some challenges,such as short transmission distance,high frequency band requirements,and poor anti-interference ability.In order to overcome these problems,the equalizer has been widely used as an important signal processing device.The equalizer can compensate the received signal,improve the signal quality,and thus enhance the transmission performance of the system.With the trend of increasing communication rate,the PAM4 high-speed serial signal receiving equalizer studied in this thesis has important significance for high-speed serial communication systems.This thesis designs a PAM4 serial signal receiving equalizer with a rate of 40 Gbps.The chip consists of a continuous time linear equalizer(CTLE)module,a level decision module,a half-rate decision feedback equalizer module,a decoder module and a bandgap Baseline module composition.In the design of the continuous-time linear equalizer module,this thesis adopts the degenerated structure of source capacitance,and analyzes and verifies the circuit characteristics.The simulation shows that the continuous-time linear equalizer circuit has good bandwidth.Secondly,in view of the difference between PAM4 signal and traditional NRZ signal,PAM4 signal has four-level characteristics.This thesis designs a level judgment circuit to shift and limit the equalized PAM4 signal to generate an upper,middle and lower three-way thermometer.code.In addition,in order to improve the compensation ability of the PAM4 equalizer for channel attenuation,this thesis propose using two-tap odd-even dualchannel decision feedback equalizer,including an adder,a CML latch and a multiplexer,and effectively improves the equalization effect by using a half-rate sampling clock,and reduces the power consumption of the equalizer.In this thesis,the layout design of the overall circuit is completed by 40 nm CMOS technology,and the layout area is 140 μm×200 μm.Simulation results show that in the case of insertion channel loss of 12.6 d B,the eye diagram of the PAM4 signal after CTLE equalization has been significantly opened,and the eye width has reached 29 ps(0.58 UI).The peak-to-peak jitter of the two non-return-to-zero signals decoded by the final equalizer is 4.2 ps(0.08 UI),the power consumption is 78 m W at a power supply voltage of 1.2 V,and the power efficiency is 1.98 p J/b,which has high energy efficiency.