Design Of A Dual Channel Digital To Analog Converter In 40 Nm Technology

At present,the new generation of wireless communication system(5G)under construction requires higher data throughput,faster response time and lower power consumption.As a key part of wireless communication system,data converter is also developing towards high performance and low power consumption.Current-steering structure,which is compatible with standard CMOS technology and supports high sampling rate,has always been the mainstream of high-speed and high-precision digital-to-analog converter(DAC).Moreover,it can also achieve low power consumption through low-voltage current-mode technology.Therefore,it is of great significance to study current steering DAC with high performance and low power consumption.A 10-bit dual-channel current steering DAC based on TSMC40nm CMOS process is designed in this paper.The model,circuit,layout and test are analyzed in detail.Firstly,this paper discusses the development history and research significance of DAC at home and abroad,expounds the basic working principle,main classification and characteristic parameters of DAC,and summarizes the advantages of current-steering structure.Then,by analyzing the influence of the segment ratio on the performance and area of DAC,the piecewise structure of thermometer code for the higher 6 bits and binary code for the lower 4 bits is determined,and the ideal behavior level model and corresponding error model of the DAC are established under the SIMULINK environment.With the help of the above model,the effects of mismatch error of current source,limited output impedance and clock feed-through effect of switch on the dynamic characteristics of DAC are analyzed.Secondly,the circuit design process of DAC main modules such as current reference circuit,unit current source circuit,switch driver circuit,6-63 decoder is introduced one by one.The overall layout of DAC and layout mode of current source array are given.The ladder symmetrical layout and Tree-H power line layout used in current source array are analyzed in detail.Finally,the overall test scheme of the chip is proposed,and the key point test method aiming at linear error is emphatically analyzed,and the chip test is completed.The test results show the differential nonlinearity(DNL)of the DAC is less than 0.52 LSB and the integral nonlinearity(INL)is less than 0.5 LSB.When a full swing sine wave with a frequency of 1 MHz and a clock sampling frequency of 32 MHz is applied to the input,the signal-to-noise ratio(SNR)of the DAC is 58.02 dB and the spurious dynamic range(SFDR)is 72.2 dB.The test results show that the dynamic characteristics of the DAC at low frequencies are quite good.When the input signal frequency is 5 MHz and the clock sampling frequency is 32 MHz,the SFDR of DAC is 66.15 dB,which meets the requirements of design specifications,but the dynamic characteristics of DAC at high frequencies need to be further improved.The effective area of the DAC chip is 0.15 mm~2and the power consumption is less than 6 mW.