Design Of Low Phase Noise And Low Power Consumption CMOS Voltage-Controlled Oscillator

Voltage-controlled oscillator is an important part of transceivers in wireless communication system and radar system,whose performance determines the function of the whole system to a certain extent.Especially phase noise and power consumption,they directly affect the figure of merit that evaluates the overall performance of the oscillator.They are important indicators for designing voltage-controlled oscillator.This paper focuses on the topic of "the design of low phase noise and low power consumption CMOS voltage-controlled oscillator ".The main work includes(1)a literature review of important literature related to inductor and capacitor based voltagecontrolled oscillator published in the last two decades has been conducted.This part analyzes the main performance indexes of inductor and capacitor based voltagecontrolled oscillator such as phase noise,frequency tuning range,power consumption,efficiency and output power.And then,the methods and techniques for performance improvement for different performance parameters are classified and summarized.At last,the performance trends of the voltage-controlled oscillator over time are summarized.(2)The design of low phase noise and low power consumption continuous tuning dual-core voltage-controlled oscillator for frequency modulated continuous wave radar systems.Low phase noise is achieved by dual core operation with a wide continuous frequency tuning range.In order to reduce the high power consumption caused by the dual cores,we adopt current reused technique of center-tapped transformer coupled buffer amplifier.It achieves an improvement in the the figure of merit of dual-core voltage-controlled oscillator.At the same time,a higher output power is achieved,and the power efficiency is greatly improved.This circuit is designed in GF 55 nm CMOS technology.The different simulation softwares are used for Cosimulation.Circuit schematic simulation and layout design have been completed.(3)The design of low phase noise and low power consumption complementary class F voltage-controlled oscillator.The proposed voltage-controlled oscillator is coupled to an auxiliary tank by a transformer,which increases the third-harmonic through an extra impedance peak.A pseudo square wave voltage waveform is formed near the inductor and capacitor based tank.The voltage-controlled oscillator's effective noise factor decreases due the reducing of the effective impulse sensitivity function.Combining the complementary structure minimizes the phase noise and power consumption of the voltage-controlled oscillator,and realizes the maximum the figure of merit of the Kband voltage-controlled oscillator.This circuit is designed in GF 55 nm CMOS technology.The different simulation softwares are used for Co-simulation.Circuit schematic simulation and layout design have been completed.