| Due to the rapid development of advanced technologies such as the Internet of Things and5 G communication,the number of wireless communication terminals increased rapidly,greatly increasing the risk of blocking.If the receiver blocking resistance is poor and the signal blockage occurs,then the performance of the circuit will deteriorate seriously.Therefore,it is very important to improve the anti-blocking performance of the receiver.An anti-blocking down-conversion mixer circuit with operating frequency of 2.4?5.3GHz based on 22 nm CMOS process is presented in this thesis,which is mainly composed of four modules: passive switch pair,four-phase local oscillator signal generation circuit,baseband capacitance and baseband amplification circuit.Because the passive switch has frequency conversion loss,the baseband amplification circuit is used to amplify the baseband signal to provide a certain gain.The four-phase non-interlaced square wave local oscillator signal with25% duty cycle is generated by the four-phase local oscillator signal generation circuit,which improves the performance of the down-conversion mixer.Baseband capacitor and passive switch pair form impedance transfer network,thus realizing the function of impedance transfer.The circuit design,pre-simulation,layout design and post-simulation are presented.The postsimulation results show that under 1V power supply voltage,in the 2.4?5.3GHz operating frequency,the baseband bandwidth is larger than 51 MHz,the voltage conversion gain is larger than 9.2d B,the double-sideband noise figure is less than 8.9d B,and the in-band input 1d B compression point is larger than-8.5d Bm.The blocking signal rejection ratio at the frequency deviation of 400 MHz is larger than 8.3d B,and the operating current is less than 6.5m A.The 2.4?5.3GHz anti-blocking down-conversion mixer circuit designed in this thesis has higher gain,lower noise and better anti-blocking performance.After verification,it can be used in broadband transceiver system chip. |
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